dsleung

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-20 12:52:23 +08:00

b9e4279ffe Replace nMigen copy with shell.nix config file

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-20 12:00:41 +08:00

a6b4891a38 Add causal checks

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-20 11:10:45 +08:00

2a9ddf0868 Add register checks

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-19 17:22:11 +08:00

2383706012 Add PC backward checks

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-19 17:00:22 +08:00

2bfd909b49 Add PC forward checks

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-19 14:58:10 +08:00

f7ddbf8cd8 Fix broken markdown in README.md

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-19 14:56:42 +08:00

c073411bd2 Add tests for all RV32I instructions

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-18 14:11:00 +08:00

0e0d4b6e42 Add (currently failing) test case for LUI instruction

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-17 16:46:33 +08:00

3faa8ed1b8 Add build instructions for Minerva

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-17 16:03:28 +08:00

7005d22e4e Add instruction check

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-17 12:06:00 +08:00

d749b297cf Update README.md

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-17 11:51:13 +08:00

73707afe78 Modularize codebase

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-13 17:38:15 +08:00

1982668829 Add Minerva core, to be integrated later

dsleung deleted branch restructuring from M-Labs/riscv-formal-nmigen

2020-08-13 15:20:43 +08:00

dsleung pushed to master at M-Labs/riscv-formal-nmigen

2020-08-13 15:20:35 +08:00

6459c71ac5 Merge pull request 'Restructure insns directory contents' (#2) from restructuring into master

f358e0679a Rename module names to follow PEP8

4d211bb24a Update README.md

40344f7841 Add RV32I base ISA

28949f36f4 Fix typo in InsnSw.py

Compare 110 commits »

dsleung merged pull request M-Labs/riscv-formal-nmigen#2

2020-08-13 15:20:35 +08:00

Restructure insns directory contents

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-13 15:15:04 +08:00

f358e0679a Rename module names to follow PEP8

dsleung created pull request M-Labs/riscv-formal-nmigen#2

2020-08-13 14:32:30 +08:00

Restructure insns directory contents

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-13 14:28:49 +08:00

4d211bb24a Update README.md

dsleung pushed to restructuring at M-Labs/riscv-formal-nmigen

2020-08-13 14:24:03 +08:00

40344f7841 Add RV32I base ISA