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zynq-rs
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635 Commits 4 Branches 0 Tags 1.2 MiB
Commit Graph

11 Commits

Author SHA1 Message Date
Brad Bondurant 188954ddc7 zynq_us: clocks (WIP) 2022-11-17 15:46:27 -05:00
Brad Bondurant 0f2376410f zynq_us/slcr: add type enums for clksel fields 2022-11-17 15:44:11 -05:00
Brad Bondurant 2e5f7ec2f7 zynq_us/slcr: make `unlocked` method a trait 2022-11-17 15:42:31 -05:00
Brad Bondurant c2455b1cda zynq_us/slcr: add crl_apb definitions 2022-11-17 09:04:15 -05:00
Brad Bondurant 1e50f68f41 zynq_us/slcr: move common register types to their own file 2022-11-17 09:00:40 -05:00
Brad Bondurant c3273a6ff8 [nfc]zynq_us/slcr: rename pll regs 2022-11-16 09:08:21 -05:00
Brad Bondurant 20784803f0 zync_us: add lib.rs 2022-11-16 08:57:45 -05:00
Brad Bondurant 79a0d72976 zync_us/slcr: add MIO SLCRs 2022-11-16 08:54:05 -05:00
Brad Bondurant 2b3045b46c zync_us: start defining SLCR blocks 2022-11-15 16:20:09 -05:00
Brad Bondurant 2c179841be zynq_us/uart: same register fields as zynq, just a different location 
BDIV_MIN/MAX and CD_MAX are also the same
 2022-11-15 16:14:42 -05:00
Brad Bondurant 508fac66e8 add crate for ultrascale+ drivers 2022-11-15 16:05:29 -05:00