forked from M-Labs/zynq-rs
zynq_us/slcr: add type enums for clksel fields
parent
2e5f7ec2f7
commit
0f2376410f
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@ -3,12 +3,18 @@
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use volatile_register::{RO, RW, WO};
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use libregister::{
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register, register_at,
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register_bit, register_bits,
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register_bit, register_bits, register_bits_typed,
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RegisterW,
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};
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use super::common::{SlcrRegisterBlock, WProt, PllCfg, PllCtrl, PllFracCfg};
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#[repr(u8)]
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pub enum ApuClkSource {
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ApuPll = 0b00,
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DdrPll = 0b10,
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VideoPll = 0b11,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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// CRF_APB
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@ -24,7 +30,7 @@ pub struct RegisterBlock {
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pub ddr_pll_ctrl: PllCtrl,
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pub ddr_pll_cfg: PllCfg,
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pub ddr_pll_frac_cfg: PllFracCfg,
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pub video_pll_ctr: PllCtrl,
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pub video_pll_ctrl: PllCtrl,
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pub video_pll_cfg: PllCfg,
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pub video_pll_frac_cfg: PllFracCfg,
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pub pll_status: PllStatus,
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@ -85,10 +91,7 @@ register!(apu_clk_ctrl, ApuClkCtrl, RW, u32);
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register_bit!(apu_clk_ctrl, clkact_half, 25);
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register_bit!(apu_clk_ctrl, clkact_full, 24);
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register_bits!(apu_clk_ctrl, divisor0, u8, 8, 13);
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// 000: APU PLL
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// 010: DDR PLL
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// 011: Video PLL
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register_bits!(apu_clk_ctrl, srcsel, u8, 0, 2);
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register_bits_typed!(apu_clk_ctrl, srcsel, u8, ApuClkSource, 0, 2);
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register!(ddr_clk_ctrl, DdrClkCtrl, RW, u32);
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register_bits!(ddr_clk_ctrl, divisor0, u8, 8, 13);
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@ -3,11 +3,27 @@
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use volatile_register::{RO, RW, WO};
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use libregister::{
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register, register_at,
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register_bit, register_bits,
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register_bit, register_bits, register_bits_typed,
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};
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use super::common::{SlcrRegisterBlock, WProt, PllCfg, PllCtrl, PllFracCfg};
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/// Clock source selection for IO-type devices
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#[repr(u8)]
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pub enum IoClkSource {
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IoPll = 0b00,
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RpuPll = 0b10,
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DdrPllToLpd = 0b11,
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}
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/// Clock source selection for RPU and related (e.g. LPD interconnect) devices
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#[repr(u8)]
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pub enum RpuClkSource {
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RpuPll = 0b00,
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IoPll = 0b10,
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DdrPllToLpd = 0b11,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub err_ctrl: RW<u32>,
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@ -26,8 +42,8 @@ pub struct RegisterBlock {
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pub rpu_pll_frac_cfg: PllFracCfg,
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reserved3: [u32; 1],
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pub pll_status: PllStatus,
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pub io_pll_to_lpd_ctrl: PllToFpdCtrl,
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pub rpu_pll_to_lpd_ctrl: PllToFpdCtrl,
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pub io_pll_to_fpd_ctrl: PllToFpdCtrl,
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pub rpu_pll_to_fpd_ctrl: PllToFpdCtrl,
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pub usb3_clk_ctrl: UsbClkCtrl,
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pub gem0_clk_ctrl: GemClkCtrl,
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pub gem1_clk_ctrl: GemClkCtrl,
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@ -48,7 +64,7 @@ pub struct RegisterBlock {
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pub rpu_clk_ctrl: RpuClkCtrl,
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reserved5: [u32; 2],
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pub iou_switch_clk_ctrl: IouSwitchClkCtrl,
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pub csu_pll_ctrl: CsuPllCtrl,
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pub csu_clk_ctrl: CsuPllCtrl,
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pub pcap_clk_ctrl: PcapClkCtrl,
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pub lpd_switch_clk_ctrl: LpdSwitchClkCtrl,
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pub lpd_lsbus_clk_ctrl: LpdLsbusClkCtrl,
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@ -166,66 +182,65 @@ register_bit!(gem_clk_ctrl, rx_clkact, 26);
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register_bit!(gem_clk_ctrl, clkact, 25);
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register_bits!(gem_clk_ctrl, divisor1, u8, 16, 21);
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register_bits!(gem_clk_ctrl, divisor0, u8, 8, 13);
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// 000: IOPLL
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// 010: RPLL
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// 011: DPLL_CLK_TO_LPD
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register_bits!(gem_clk_ctrl, srcsel, u8, 0, 2);
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register_bits_typed!(gem_clk_ctrl, srcsel, u8, IoClkSource, 0, 2);
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register!(usb_clk_ctrl, UsbClkCtrl, RW, u32);
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register_bit!(usb_clk_ctrl, clkact, 25);
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register_bits!(usb_clk_ctrl, divisor1, u8, 16, 21);
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register_bits!(usb_clk_ctrl, divisor0, u8, 8, 13);
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register_bits!(usb_clk_ctrl, srcsel, u8, 0, 2);
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register_bits_typed!(usb_clk_ctrl, srcsel, u8, IoClkSource, 0, 2);
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macro_rules! dual_div_clk_reg {
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($mod_name: ident, $struct_name: ident) => {
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($mod_name: ident, $struct_name: ident, $srcsel_type: ident) => {
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register!($mod_name, $struct_name, RW, u32);
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register_bit!($mod_name, clkact, 24);
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register_bits!($mod_name, divisor1, u8, 16, 21);
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register_bits!($mod_name, divisor0, u8, 8, 13);
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register_bits!($mod_name, srcsel, u8, 0, 2);
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register_bits_typed!($mod_name, srcsel, u8, $srcsel_type, 0, 2);
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};
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}
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dual_div_clk_reg!(qspi_clk_ctrl, QSpiClkCtrl);
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dual_div_clk_reg!(sdio_clk_ctrl, SdioClkCtrl);
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dual_div_clk_reg!(uart_clk_ctrl, UartClkCtrl);
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dual_div_clk_reg!(spi_clk_ctrl, SpiClkCtrl);
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dual_div_clk_reg!(can_clk_ctrl, CanClkCtrl);
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dual_div_clk_reg!(nand_clk_ctrl, NandClkCtrl);
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dual_div_clk_reg!(pl_clk_ctrl, PlClkCtrl);
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dual_div_clk_reg!(gem_tsu_clk_ctrl, GemTsuClkCtrl);
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dual_div_clk_reg!(ps_sysmon_clk_ctrl, PsSysmonClkCtrl);
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dual_div_clk_reg!(i2c_clk_ctrl, I2cClkCtrl);
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dual_div_clk_reg!(qspi_clk_ctrl, QSpiClkCtrl, IoClkSource);
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dual_div_clk_reg!(sdio_clk_ctrl, SdioClkCtrl, IoClkSource);
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dual_div_clk_reg!(uart_clk_ctrl, UartClkCtrl, IoClkSource);
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dual_div_clk_reg!(spi_clk_ctrl, SpiClkCtrl, IoClkSource);
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dual_div_clk_reg!(can_clk_ctrl, CanClkCtrl, IoClkSource);
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dual_div_clk_reg!(nand_clk_ctrl, NandClkCtrl, IoClkSource);
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dual_div_clk_reg!(pl_clk_ctrl, PlClkCtrl, IoClkSource);
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dual_div_clk_reg!(gem_tsu_clk_ctrl, GemTsuClkCtrl, IoClkSource);
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dual_div_clk_reg!(ps_sysmon_clk_ctrl, PsSysmonClkCtrl, RpuClkSource);
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dual_div_clk_reg!(i2c_clk_ctrl, I2cClkCtrl, IoClkSource);
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register!(rpu_clk_ctrl, RpuClkCtrl, RW, u32);
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register_bit!(rpu_clk_ctrl, clkact_core, 25);
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register_bit!(rpu_clk_ctrl, clkact, 24);
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register_bits!(rpu_clk_ctrl, divisor0, u8, 8, 13);
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register_bits!(rpu_clk_ctrl, srcsel, u8, 0, 2);
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register_bits_typed!(rpu_clk_ctrl, srcsel, u8, RpuClkSource, 0, 2);
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macro_rules! single_div_clk_reg {
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($mod_name: ident, $struct_name: ident) => {
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// default to RpuClkSource
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($mod_name: ident, $struct_name: ident, $srcsel_type: ident) => {
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register!($mod_name, $struct_name, RW, u32);
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register_bit!($mod_name, clkact, 24);
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register_bits!($mod_name, divisor1, u8, 16, 21);
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register_bits!($mod_name, divisor0, u8, 8, 13);
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register_bits!($mod_name, srcsel, u8, 0, 2);
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register_bits_typed!($mod_name, srcsel, u8, $srcsel_type, 0, 2);
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};
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}
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single_div_clk_reg!(iou_switch_clk_ctrl, IouSwitchClkCtrl);
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single_div_clk_reg!(csu_pll_ctrl, CsuPllCtrl);
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single_div_clk_reg!(pcap_clk_ctrl, PcapClkCtrl);
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single_div_clk_reg!(lpd_switch_clk_ctrl, LpdSwitchClkCtrl);
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single_div_clk_reg!(lpd_lsbus_clk_ctrl, LpdLsbusClkCtrl);
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single_div_clk_reg!(dbg_lpd_clk_ctrl, DbgLpdClkCtrl);
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single_div_clk_reg!(lpd_dma_clk_ctrl, LpdDmaClkCtrl);
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single_div_clk_reg!(timestamp_clk_ctrl, TimestampClkCtrl);
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single_div_clk_reg!(iou_switch_clk_ctrl, IouSwitchClkCtrl, RpuClkSource);
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single_div_clk_reg!(csu_clk_ctrl, CsuPllCtrl, IoClkSource);
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single_div_clk_reg!(pcap_clk_ctrl, PcapClkCtrl, IoClkSource);
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single_div_clk_reg!(lpd_switch_clk_ctrl, LpdSwitchClkCtrl, RpuClkSource);
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single_div_clk_reg!(lpd_lsbus_clk_ctrl, LpdLsbusClkCtrl, RpuClkSource);
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single_div_clk_reg!(dbg_lpd_clk_ctrl, DbgLpdClkCtrl, RpuClkSource);
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single_div_clk_reg!(lpd_dma_clk_ctrl, LpdDmaClkCtrl, RpuClkSource);
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// todo: timestamp clk can also run directly from PS_REF_CLK (0b1xx)
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single_div_clk_reg!(timestamp_clk_ctrl, TimestampClkCtrl, IoClkSource);
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register!(pl_thr_ctrl, PlThrCtrl, RW, u32);
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