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astro pushed to flarum at astro/it-infra 2020-08-22 08:25:52 +08:00
24e1201ab1 flarum: init
4af23a3307 flarum: init
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astro created pull request M-Labs/it-infra#5 2020-08-22 08:07:59 +08:00
flarum: init
astro pushed to flarum at astro/it-infra 2020-08-22 08:00:02 +08:00
4af23a3307 flarum: init
b8dae38b00 update SSH keys
4d8214d00e nixbld: open firewall for jitsi-videobridge
420796a547 nixbld: install jitsi
5322606804 disable homu
astro pushed to split-software-gateware-builds at M-Labs/nix-scripts 2020-08-21 05:52:42 +08:00
b14fa8d9d0 artiq-fast: build gateware from a self-contained separate source derivation
82ff5added artiq-full: make luh 6+ only (fastino)
51ecc65edc disable wipm4
536e26b771 zc706 -> zynq-rs
a7179589bd su variant: disable
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astro pushed to master at M-Labs/zynq-rs 2020-08-18 01:39:15 +08:00
b268fe015a stdio::drop_uart(): add delay
astro pushed to master at M-Labs/artiq-zynq 2020-08-18 01:21:38 +08:00
bb35d6b46a default.nix: update cargosha256
astro pushed to master at M-Labs/artiq-zynq 2020-08-18 01:19:02 +08:00
760f46a115 update dependencies
astro pushed to master at M-Labs/zynq-rs 2020-08-17 23:38:22 +08:00
64db9b0142 Merge pull request 'libboard_zynq: dead code, peripheral & regblock ctor names consistency' (#63) from harry/zynq-rs:cleanup into master
1a96a7550a libboard_zynq: make RegisterBlock constructors more consistent
36947104e3 libboard_zynq: make constructor names more consistent
11089d8a64 i2c: delete dead code
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astro pushed to master at M-Labs/zynq-rs 2020-08-17 07:04:12 +08:00
4b258c19f5 libasync: improve scheduling fairness between block_on and spawned tasks
astro pushed to eth-uncached-buffers at astro/zynq-rs 2020-08-12 06:51:53 +08:00
7c8ec46c8f eth: use UncachedSlice for both desc and buffers
astro pushed to eth-stats at astro/zynq-rs 2020-08-12 06:51:39 +08:00
4158906122 eth: collect some stats
astro pushed to eth at astro/zynq-rs 2020-08-12 06:51:29 +08:00
8267acfcba eth: latter tuning
7ae8be58cf eth: fix cache maintenance
7f3e75e20c mmu: set L2-bufferable for DDR
8c26974816 eth: warn on tx ring overflow
c86d8b2af2 experiments: setup_l2cache(), add bandwidth tester
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astro created repository astro/zynq-rs 2020-08-12 06:43:36 +08:00
astro pushed to gic at M-Labs/zynq-rs 2020-07-31 06:02:25 +08:00
96b16d2c6c gic: start implementation
d18021fc5c libboard_zynq/mpcore: added generated register definitions
astro pushed to master at M-Labs/zynq-rs 2020-07-30 03:50:13 +08:00
1f05e6977e eth::phy: replace ExtendedStatus with PSSR
e408a8b22d eth::phy::extended_status: fix cap_1000base_x_full() bit position
27effb6257 eth::phy: s/Marvel/Marvell/
de5f605d60 eth: refactor peripheral instance into type parameter, improve clock setup
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astro pushed to master at M-Labs/zynq-rs 2020-07-28 06:43:55 +08:00
ef4fb598fb ddr: improve dci divisors calculation
astro pushed to master at M-Labs/artiq-zynq 2020-07-28 01:56:38 +08:00
b388b529ad dyld: remove KERNEL_EXIDX_START/END globals, move dl_unwind_find_exidx() into runtime::kernel::core1
astro pushed to master at M-Labs/artiq-zynq 2020-07-27 08:00:47 +08:00
641204425e dyld: obtain EXIDX offsets from section headers
astro deleted branch dyld-keep-exidx from M-Labs/artiq-zynq 2020-07-25 10:39:15 +08:00
astro pushed to master at M-Labs/nix-scripts 2020-07-24 10:06:29 +08:00
be5787ab55 conda-windows/binutils-recipe: change to --build=x86_64-w64-mingw32
bc447638a9 Revert "conda-windows-binutils-or1k: build with msys2, not conda"
7f32f8e438 Revert "conda-windows-binutils-arm: likewise"
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