zynq-rs/libboard_zynq/src/devc/mod.rs

use core::fmt;
use libregister::*;
mod regs;

use crate::println;

pub struct DevC {
    regs: &'static mut regs::RegisterBlock,
}

impl DevC {
    pub fn new() -> Self {
        DevC {
            regs: regs::RegisterBlock::devc(),
        }
    }

    pub fn enable_and_select_pcap(&mut self) {
        self.regs.control.modify(|_, w| {
            w.pcap_mode(true)
             .pcap_pr(true)
        })
    }

    pub fn enable_and_select_icap(&mut self) {
        self.regs.control.modify(|_, w| {
            w.pcap_mode(true)
            .pcap_pr(false)
        })
    }

    pub fn clear_interrupts(&mut self) {
        self.regs.int_sts.modify(|_, w| {
            w.pps_gts_usr_b_int(true)
             .pps_fst_cfg_b_int(true)
             .pps_gpwrdwn_b_int(true)
             .pps_gts_cfg_b_int(true)
             .pps_cfg_reset_b_int(true)
             .ixr_axi_wto(true)
             .ixr_axi_werr(true)
             .ixr_axi_rto(true)
             .ixr_axi_rerr(true)
             .ixr_rx_fifo_ov(true)
             .ixr_wr_fifo_lvl(true)
             .ixr_rd_fifo_lvl(true)
             .ixr_dma_cmd_err(true)
             .ixr_dma_q_ov(true)
             .ixr_dma_done(true)
             .ixr_d_p_done(true)
             .ixr_p2d_len_err(true)
             .ixr_pcfg_hmac_err(true)
             .ixr_pcfg_seu_err(true)
             .ixr_pcfg_por_b(true)
             .ixr_pcfg_cfg_rst(true)
             .ixr_pcfg_done(true)
             .ixr_pcfg_init_pe(true)
             .ixr_pcfg_init_ne(true)
        })
    }

    pub fn initialize_pl(&mut self) {
        self.regs.mctrl.modify(|_, w| {
            w.pcfg_por_b(true)
             .pcfg_por_b(false)
        });
        self.wait_for_status_pcfg_init_to_be(false);
        self.regs.mctrl.modify(|_, w| {
            w.pcfg_por_b(true)
        });
        self.regs.int_sts.modify(|_,w| {
            w.ixr_pcfg_done(true)
        });
    }

    pub fn wait_for_pl_to_be_ready(&self) {
        self.wait_for_status_pcfg_init_to_be(true)
    }

    pub fn wait_for_command_queue_space(&self){
        self.wait_for_status_dma_cmd_q_f_to_be(false);
    }

    pub fn disable_pcap_loopback(&mut self) {
        self.regs.mctrl.modify(|_,w| {
            w.pcap_lpbk(false)
        });
    }

    pub fn enable_pcap_secure_mode(&mut self) {
        self.regs.control.modify(|_, w| {
            w.pcap_rate_en(true)
        });
    }
    pub fn enable_pcap_non_secure_mode(&mut self) {
        self.regs.control.modify(|_, w| {
            w.pcap_rate_en(false)
        });
    }

    pub fn wait_for_dma_transfer(&self) {
        self.wait_for_int_sts_ixr_dma_done_to_be(true);
    }

    fn wait_for_status_pcfg_init_to_be(&self, value: bool) {
        loop {
            let status = self.regs.status.read();
            println!("expected value: {}, actual pcfg_init: {}",value, status.pcfg_init());
            if value == status.pcfg_init() {
                return
            }
        }
    }

    fn wait_for_status_dma_cmd_q_f_to_be(&self, value: bool) {
        loop {
            let status = self.regs.status.read();
            if value == status.pcfg_init() {
                return
            }
        }
    }

    fn wait_for_int_sts_ixr_dma_done_to_be(&self, value: bool) {
        loop {
            let int_sts = self.regs.int_sts.read();
            if value == int_sts.ixr_dma_done() {
                return
            }
        }
    }
}