2020-01-20 19:26:29 +08:00
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use core::fmt;
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use libregister::*;
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mod regs;
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2020-01-23 05:06:04 +08:00
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use crate::println;
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2020-01-20 19:26:29 +08:00
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pub struct DevC {
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regs: &'static mut regs::RegisterBlock,
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}
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impl DevC {
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pub fn new() -> Self {
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DevC {
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regs: regs::RegisterBlock::devc(),
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}
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}
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2020-01-23 05:06:04 +08:00
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pub fn enable_and_select_pcap(&mut self) {
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2020-01-20 19:26:29 +08:00
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self.regs.control.modify(|_, w| {
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w.pcap_mode(true)
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2020-01-23 05:06:04 +08:00
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.pcap_pr(true)
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2020-01-20 19:26:29 +08:00
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})
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}
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2020-01-23 05:06:04 +08:00
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pub fn enable_and_select_icap(&mut self) {
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2020-01-20 19:26:29 +08:00
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self.regs.control.modify(|_, w| {
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2020-01-23 05:06:04 +08:00
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w.pcap_mode(true)
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2020-01-20 19:26:29 +08:00
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.pcap_pr(false)
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})
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}
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2020-01-23 05:06:04 +08:00
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pub fn clear_interrupts(&mut self) {
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self.regs.int_sts.modify(|_, w| {
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w.pps_gts_usr_b_int(true)
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.pps_fst_cfg_b_int(true)
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.pps_gpwrdwn_b_int(true)
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.pps_gts_cfg_b_int(true)
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.pps_cfg_reset_b_int(true)
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.ixr_axi_wto(true)
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.ixr_axi_werr(true)
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.ixr_axi_rto(true)
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.ixr_axi_rerr(true)
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.ixr_rx_fifo_ov(true)
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.ixr_wr_fifo_lvl(true)
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.ixr_rd_fifo_lvl(true)
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.ixr_dma_cmd_err(true)
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.ixr_dma_q_ov(true)
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.ixr_dma_done(true)
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.ixr_d_p_done(true)
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.ixr_p2d_len_err(true)
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.ixr_pcfg_hmac_err(true)
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.ixr_pcfg_seu_err(true)
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.ixr_pcfg_por_b(true)
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.ixr_pcfg_cfg_rst(true)
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.ixr_pcfg_done(true)
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.ixr_pcfg_init_pe(true)
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.ixr_pcfg_init_ne(true)
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})
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}
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pub fn initialize_pl(&mut self) {
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self.regs.mctrl.modify(|_, w| {
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w.pcfg_por_b(true)
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.pcfg_por_b(false)
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});
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self.wait_for_status_pcfg_init_to_be(false);
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self.regs.mctrl.modify(|_, w| {
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w.pcfg_por_b(true)
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});
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self.regs.int_sts.modify(|_,w| {
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w.ixr_pcfg_done(true)
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});
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}
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pub fn wait_for_pl_to_be_ready(&self) {
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self.wait_for_status_pcfg_init_to_be(true)
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}
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pub fn wait_for_command_queue_space(&self){
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self.wait_for_status_dma_cmd_q_f_to_be(false);
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}
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pub fn disable_pcap_loopback(&mut self) {
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self.regs.mctrl.modify(|_,w| {
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w.pcap_lpbk(false)
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});
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}
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pub fn enable_pcap_secure_mode(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_rate_en(true)
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});
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}
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pub fn enable_pcap_non_secure_mode(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_rate_en(false)
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});
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}
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pub fn wait_for_dma_transfer(&self) {
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self.wait_for_int_sts_ixr_dma_done_to_be(true);
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}
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fn wait_for_status_pcfg_init_to_be(&self, value: bool) {
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loop {
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let status = self.regs.status.read();
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println!("expected value: {}, actual pcfg_init: {}",value, status.pcfg_init());
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if value == status.pcfg_init() {
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return
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}
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}
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}
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fn wait_for_status_dma_cmd_q_f_to_be(&self, value: bool) {
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loop {
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let status = self.regs.status.read();
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if value == status.pcfg_init() {
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return
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}
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}
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}
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fn wait_for_int_sts_ixr_dma_done_to_be(&self, value: bool) {
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loop {
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let int_sts = self.regs.int_sts.read();
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if value == int_sts.ixr_dma_done() {
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return
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}
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}
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}
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2020-01-20 19:26:29 +08:00
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}
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