forked from M-Labs/zynq-rs
56 lines
1.2 KiB
Markdown
56 lines
1.2 KiB
Markdown
# Bare-metal Rust on Zynq-7000
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Supported features:
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* Clocking setup
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* UART
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* SDRAM setup
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* Ethernet with smoltcp and async-await on TCP sockets
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* SD card
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* PL programming and startup
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* Pure Rust SZL first-stage bootloader, with SD boot and netboot
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* Control of second CPU core and message passing, with async-await support
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Supported boards:
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* ZC706
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* Red Pitaya
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* Cora Z7-10 (seems to also run on Cora Z7-07S, including dual-core support)
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## Build
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```shell
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nix-shell --command "cargo xbuild --release -p experiments"
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```
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Currently the ELF output is placed at `target/armv7-none-eabihf/release/experiments`
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## Debug
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### Running on the ZC706
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```shell
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nix-shell --command "cargo xbuild --release -p experiments"
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cd openocd
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openocd -f zc706.cfg
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```
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### Running on the Cora Z7-10
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```shell
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nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
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cd openocd
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openocd -f cora-z7-10.cfg
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```
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### Loading a bitstream into volatile memory
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```shell
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openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"
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```
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## License
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Copyright (C) 2019-2021 M-Labs Limited.
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Released under the GNU LGPL v3. See the LICENSE file for details.
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