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zynq-rs
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474 Commits

Author SHA1 Message Date
Astro 6ffcf7d4a4 ram: lock for concurrent use 
this may be reverted if ram allocation shall be more separate.
 2019-11-20 17:25:54 +01:00
Astro 4f8a76e29b stdio: lock for use by core1 2019-11-20 17:00:57 +01:00
Astro ff41f4dd2d cortex_a9::mutex: restore and fix powersaving behaviour, doc 2019-11-20 16:30:56 +01:00
Astro d89f594ba4 cortex_a9::mutex: use AtomU32, remove powersaving behavior 
Mutex works properly now.
 2019-11-18 02:37:59 +01:00
Astro 4e4ff512d9 add cortex_a9::mutex 2019-11-18 02:13:54 +01:00
Astro 85f29ace6b boot: flush cache-line 2019-11-18 01:22:57 +01:00
Astro ef6d0ff3f1 boot: reset core1 before start 2019-11-18 00:38:03 +01:00
Astro 0bc941d789 main: start_core1 2019-11-16 00:53:30 +01:00
Astro a416f48af1 main: add empty main_core1() 2019-11-16 00:21:57 +01:00
Astro b6596d930d boot: ACTLR.enable_smp() 2019-11-16 00:12:58 +01:00
Astro 49901d1b8a boot: prepare core1 bootup 2019-11-15 23:59:01 +01:00
Björn Stein 4a1d0fc0c3 zynq::mpcore: add register definitions 2019-11-14 02:11:58 +01:00
Astro 50481b3a80 main: rm obsolete compile feature 2019-11-13 23:33:11 +01:00
Astro b76dc4037d main: change IP address to 192.168.1.51/24 2019-11-13 16:02:56 +01:00
Astro caa69fda2e main: refactor into boot 2019-11-11 02:46:18 +01:00
Astro 3279aab961 main: refactor into abort, panic, ram 2019-11-11 02:46:18 +01:00
Astro 92c274348f zynq::eth: enable checksum offload 2019-11-11 01:42:41 +01:00
Astro 3eb7fce572 delint 2019-11-11 01:42:38 +01:00
Astro b1472096ba main: change IP address to 192.168.1.28/24 2019-11-11 01:40:07 +01:00
Astro cb1b5776cd Cargo.lock: update dependencies 2019-11-11 00:45:59 +01:00
Astro 3496755406 update rust + smoltcp 2019-11-11 00:28:46 +01:00
Astro 959bf8a245 zynq::eth: don't check_link_change if link already established 2019-11-11 00:08:48 +01:00
Astro 4d3b2ac7e5 zynq::ddr: use different data_bus_width for targets 
DDR still works only on the zc706, not on the cora z7-10.
 2019-11-11 00:06:35 +01:00
Astro cae02947bc zynq::eth: remove all memory barriers 
They were not the solution.
 2019-11-10 23:52:55 +01:00
Astro afd96bd887 zynq::clocks: unlock slcr in enable_io() 2019-11-07 00:13:50 +01:00
Astro 261455877d zynq::ddr: fix DDR 3x/2x setup, print clocks 2019-11-07 00:13:50 +01:00
Astro ff96bf903b zynq::ddr: only enable_ddr if no clock yet 
that's only an issue for the cora z7
 2019-11-07 00:13:50 +01:00
Astro d2df5652d0 Revert "zynq: replace unnecessary slcr::unlocked with new" 
This reverts commit 6bee1f44f4.
 2019-11-07 00:13:50 +01:00
Astro eb56dda44f zynq::slcr::unlocked: fix comment 2019-11-07 00:13:50 +01:00
Sebastien Bourdeauducq 6e50b32e80 openocd: configure SRST for digilent_jtag_smt2_nc + Zynq 
Digilent docs say Zynq boards should connect it to GPIO2.

Closes #2
 2019-11-05 12:36:07 +08:00
Astro 74c43b3477 zynq::eth::tx: clear entry.word1 for each packet 2019-11-04 02:31:40 +01:00
Astro 99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed 2019-11-04 02:30:00 +01:00
Astro 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation 
off-by-one, didn't change behavior.
 2019-11-03 02:23:16 +01:00
Astro 04e816d99e zynq::slcr: fix a bitfield index 
that didn't solve our problems.
 2019-11-03 02:01:42 +01:00
Astro 6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new 2019-10-31 20:48:07 +01:00
Astro 54e4b9281f main: rewrap linked_list_allocator 2019-10-31 19:21:02 +01:00
Astro f688eb83ab default.nix: update cargoSha256 2019-10-31 03:19:39 +01:00
Astro 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell 
vcell can be initialized cleanly.
 2019-10-31 03:15:13 +01:00
Astro 1f728686ff rm ram, add linked_list_allocator on ddr 2019-10-31 01:41:10 +01:00
Astro e248d3d3b1 zynq::ddr: optimize memtest 2019-10-31 01:32:45 +01:00
Astro 91bab76ab6 zynq::ddr: fix usable ram size 2019-10-31 01:27:49 +01:00
Astro 43501003f9 openocd/zc706: decimate `adapter_khz` for reliability 2019-10-31 00:28:19 +01:00
Astro ceeaa6427e zynq::ddr: fix typo 2019-10-28 23:58:25 +01:00
Astro 7cdf6c0918 start implementation of a StaticAllocator 2019-10-28 00:43:57 +01:00
Astro fc39885d3b zynq::ddr: fix clock setup 2019-10-28 00:43:09 +01:00
Astro f199ac68b4 zynq::ddr: don't overwrite slcr.ddr_pll_ctrl 2019-10-27 22:54:34 +01:00
Astro 637bb35f43 zynq::ddr: fix memtest progress calculation 2019-10-27 20:38:35 +01:00
Astro 85bd506132 zynq::ddr: parameters 2019-10-27 20:38:06 +01:00
Astro 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage 
this seems to make DDR RAM work.
 2019-10-27 20:30:56 +01:00
Astro 9b4f07f37c zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00