DDR: fixed register write.

Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
tcp-recv-fnmut
pca006132 2020-07-06 11:40:21 +08:00 committed by Gitea
parent ae4d3e2455
commit 90904634cd
1 changed files with 1 additions and 1 deletions

View File

@ -236,7 +236,7 @@ impl DdrRam {
regs::DfiTiming::zeroed()
.rddata_en(0x6)
.ctrlup_min(0x3)
.ctrlup_max(0x4)
.ctrlup_max(0x40)
);
self.regs.phy_init_ratio3.write(