From 90904634cd6f89e7d9e48ecd06b5289e0d98b33d Mon Sep 17 00:00:00 2001
From: pca006132 <john.lck40@gmail.com>
Date: Mon, 6 Jul 2020 11:40:21 +0800
Subject: [PATCH] DDR: fixed register write.

Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
---
 libboard_zynq/src/ddr/mod.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs
index 8842140..51b20d7 100644
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@@ -236,7 +236,7 @@ impl DdrRam {
             regs::DfiTiming::zeroed()
                 .rddata_en(0x6)
                 .ctrlup_min(0x3)
-                .ctrlup_max(0x4)
+                .ctrlup_max(0x40)
         );
 
         self.regs.phy_init_ratio3.write(