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libboard_zynq: add fpgax_clk_ctrl registers

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Sebastien Bourdeauducq 2020-07-07 19:37:51 +08:00
parent e67efe439b
commit 371e59cef5
1 changed files with 24 additions and 4 deletions
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28
libboard_zynq/src/slcr.rs
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@ -102,19 +102,19 @@ pub struct RegisterBlock {
pub dbg_clk_ctrl: RW<u32>, pub dbg_clk_ctrl: RW<u32>,
pub pcap_clk_ctrl: RW<u32>, pub pcap_clk_ctrl: RW<u32>,
pub topsw_clk_ctrl: RW<u32>, pub topsw_clk_ctrl: RW<u32>,
pub fpga0_clk_ctrl: RW<u32>, pub fpga0_clk_ctrl: Fpga0ClkCtrl,
pub fpga0_thr_ctrl: RW<u32>, pub fpga0_thr_ctrl: RW<u32>,
pub fpga0_thr_cnt: RW<u32>, pub fpga0_thr_cnt: RW<u32>,
pub fpga0_thr_sta: RO<u32>, pub fpga0_thr_sta: RO<u32>,
pub fpga1_clk_ctrl: RW<u32>, pub fpga1_clk_ctrl: Fpga1ClkCtrl,
pub fpga1_thr_ctrl: RW<u32>, pub fpga1_thr_ctrl: RW<u32>,
pub fpga1_thr_cnt: RW<u32>, pub fpga1_thr_cnt: RW<u32>,
pub fpga1_thr_sta: RO<u32>, pub fpga1_thr_sta: RO<u32>,
pub fpga2_clk_ctrl: RW<u32>, pub fpga2_clk_ctrl: Fpga2ClkCtrl,
pub fpga2_thr_ctrl: RW<u32>, pub fpga2_thr_ctrl: RW<u32>,
pub fpga2_thr_cnt: RW<u32>, pub fpga2_thr_cnt: RW<u32>,
pub fpga2_thr_sta: RO<u32>, pub fpga2_thr_sta: RO<u32>,
pub fpga3_clk_ctrl: RW<u32>, pub fpga3_clk_ctrl: Fpga3ClkCtrl,
pub fpga3_thr_ctrl: RW<u32>, pub fpga3_thr_ctrl: RW<u32>,
pub fpga3_thr_cnt: RW<u32>, pub fpga3_thr_cnt: RW<u32>,
pub fpga3_thr_sta: RO<u32>, pub fpga3_thr_sta: RO<u32>,
@ -540,6 +540,26 @@ register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32);
register_bit!(lqspi_rst_ctrl, ref_rst, 1); register_bit!(lqspi_rst_ctrl, ref_rst, 1);
register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0); register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0);
register!(fpga0_clk_ctrl, Fpga0ClkCtrl, RW, u32);
register_bits!(fpga0_clk_ctrl, divisor1, u8, 20, 25);
register_bits!(fpga0_clk_ctrl, divisor0, u8, 8, 13);
register_bits_typed!(fpga0_clk_ctrl, src_sel, u8, PllSource, 4, 5);
register!(fpga1_clk_ctrl, Fpga1ClkCtrl, RW, u32);
register_bits!(fpga1_clk_ctrl, divisor1, u8, 20, 25);
register_bits!(fpga1_clk_ctrl, divisor0, u8, 8, 13);
register_bits_typed!(fpga1_clk_ctrl, src_sel, u8, PllSource, 4, 5);
register!(fpga2_clk_ctrl, Fpga2ClkCtrl, RW, u32);
register_bits!(fpga2_clk_ctrl, divisor1, u8, 20, 25);
register_bits!(fpga2_clk_ctrl, divisor0, u8, 8, 13);
register_bits_typed!(fpga2_clk_ctrl, src_sel, u8, PllSource, 4, 5);
register!(fpga3_clk_ctrl, Fpga3ClkCtrl, RW, u32);
register_bits!(fpga3_clk_ctrl, divisor1, u8, 20, 25);
register_bits!(fpga3_clk_ctrl, divisor0, u8, 8, 13);
register_bits_typed!(fpga3_clk_ctrl, src_sel, u8, PllSource, 4, 5);
register!(fpga_rst_ctrl, FpgaRstCtrl, RW, u32); register!(fpga_rst_ctrl, FpgaRstCtrl, RW, u32);
register_bit!(fpga_rst_ctrl, fpga0_out_rst, 0); register_bit!(fpga_rst_ctrl, fpga0_out_rst, 0);
register_bit!(fpga_rst_ctrl, fpga1_out_rst, 1); register_bit!(fpga_rst_ctrl, fpga1_out_rst, 1);