From 371e59cef57746e3dd4cae915be7fd3286972822 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 7 Jul 2020 19:37:51 +0800 Subject: [PATCH] libboard_zynq: add fpgax_clk_ctrl registers --- libboard_zynq/src/slcr.rs | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/libboard_zynq/src/slcr.rs b/libboard_zynq/src/slcr.rs index a0d85c9..e8e36bb 100644 --- a/libboard_zynq/src/slcr.rs +++ b/libboard_zynq/src/slcr.rs @@ -102,19 +102,19 @@ pub struct RegisterBlock { pub dbg_clk_ctrl: RW, pub pcap_clk_ctrl: RW, pub topsw_clk_ctrl: RW, - pub fpga0_clk_ctrl: RW, + pub fpga0_clk_ctrl: Fpga0ClkCtrl, pub fpga0_thr_ctrl: RW, pub fpga0_thr_cnt: RW, pub fpga0_thr_sta: RO, - pub fpga1_clk_ctrl: RW, + pub fpga1_clk_ctrl: Fpga1ClkCtrl, pub fpga1_thr_ctrl: RW, pub fpga1_thr_cnt: RW, pub fpga1_thr_sta: RO, - pub fpga2_clk_ctrl: RW, + pub fpga2_clk_ctrl: Fpga2ClkCtrl, pub fpga2_thr_ctrl: RW, pub fpga2_thr_cnt: RW, pub fpga2_thr_sta: RO, - pub fpga3_clk_ctrl: RW, + pub fpga3_clk_ctrl: Fpga3ClkCtrl, pub fpga3_thr_ctrl: RW, pub fpga3_thr_cnt: RW, pub fpga3_thr_sta: RO, @@ -540,6 +540,26 @@ register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32); register_bit!(lqspi_rst_ctrl, ref_rst, 1); register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0); +register!(fpga0_clk_ctrl, Fpga0ClkCtrl, RW, u32); +register_bits!(fpga0_clk_ctrl, divisor1, u8, 20, 25); +register_bits!(fpga0_clk_ctrl, divisor0, u8, 8, 13); +register_bits_typed!(fpga0_clk_ctrl, src_sel, u8, PllSource, 4, 5); + +register!(fpga1_clk_ctrl, Fpga1ClkCtrl, RW, u32); +register_bits!(fpga1_clk_ctrl, divisor1, u8, 20, 25); +register_bits!(fpga1_clk_ctrl, divisor0, u8, 8, 13); +register_bits_typed!(fpga1_clk_ctrl, src_sel, u8, PllSource, 4, 5); + +register!(fpga2_clk_ctrl, Fpga2ClkCtrl, RW, u32); +register_bits!(fpga2_clk_ctrl, divisor1, u8, 20, 25); +register_bits!(fpga2_clk_ctrl, divisor0, u8, 8, 13); +register_bits_typed!(fpga2_clk_ctrl, src_sel, u8, PllSource, 4, 5); + +register!(fpga3_clk_ctrl, Fpga3ClkCtrl, RW, u32); +register_bits!(fpga3_clk_ctrl, divisor1, u8, 20, 25); +register_bits!(fpga3_clk_ctrl, divisor0, u8, 8, 13); +register_bits_typed!(fpga3_clk_ctrl, src_sel, u8, PllSource, 4, 5); + register!(fpga_rst_ctrl, FpgaRstCtrl, RW, u32); register_bit!(fpga_rst_ctrl, fpga0_out_rst, 0); register_bit!(fpga_rst_ctrl, fpga1_out_rst, 1);