zynq-rs

no UART output

#28 by sb10q was closed 2020-06-13 15:11:17 +08:00

1

intermittent Ethernet lockup until power cycle

#26 by sb10q was closed 2020-07-20 10:37:58 +08:00

3

figure out way to reset Core1 from SDRAM

#24 by sb10q was closed 2020-05-07 10:46:14 +08:00

4

update rust nightly

#23 by sb10q was closed 2020-04-27 10:32:16 +08:00

1

review ZC706 SDRAM size

#22 by sb10q was closed 2020-05-09 08:37:08 +08:00

3

remove dead code from openocd scripts

#21 by sb10q was closed 2020-07-05 23:39:31 +08:00

1

rebuild when link.x is modified

#20 by sb10q was closed 2020-04-28 07:55:43 +08:00

1

graceful connection termination

#19 by sb10q was closed 2020-05-02 11:44:24 +08:00

6

use logging inside drivers

#18 by sb10q was closed 2020-05-01 07:47:09 +08:00

1

timer

#17 by sb10q was closed 2020-04-25 13:00:19 +08:00

1

use Rust logging

#16 by sb10q was closed 2020-04-21 05:40:56 +08:00

1

println! printing two newlines

#15 by sb10q was closed 2020-04-21 18:27:18 +08:00

2

Cora FPGA ID wrong

#11 by sb10q was closed 2020-05-16 07:34:36 +08:00

4

Cora build broken

#10 by sb10q was closed 2020-01-24 07:05:46 +08:00

1

rename libboard_zc706

#9 by sb10q was closed 2020-02-03 14:25:03 +08:00

2

gdb intermittently failing to connect

#8 by sb10q was closed 2020-04-17 14:08:54 +08:00

2

openocd failure Error: JTAG-DP STICKY ERROR

#7 by sb10q was closed 2020-01-10 05:16:02 +08:00

3

packet loss?

#6 by sb10q was closed 2019-11-07 13:36:54 +08:00

1

stop waiting for ethernet link on?

#5 by sb10q was closed 2019-09-29 09:23:54 +08:00

2

lock rust version

#4 by sb10q was closed 2019-09-29 05:58:40 +08:00

2

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