Cora FPGA ID wrong #11

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sb10q · 2020-01-15T15:24:22+08:00

sb10q commented

2020-01-15 15:24:22 +08:00

$ openocd -f cora-z7-10.cfg 
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 10000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Zynq CPU1.
srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: zynq.tap tap/device found: 0x13722093 (mfg: 0x049 (Xilinx), part: 0x3722, ver: 0x1)
Warn : JTAG tap: zynq.tap       UNEXPECTED: 0x13722093 (mfg: 0x049 (Xilinx), part: 0x3722, ver: 0x1)
Error: JTAG tap: zynq.tap  expected 1 of 1: 0x13723093 (mfg: 0x049 (Xilinx), part: 0x3723, ver: 0x1)
Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)

```text $ openocd -f cora-z7-10.cfg Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html none separate adapter speed: 10000 kHz Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. Zynq CPU1. srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" Info : clock speed 10000 kHz Info : JTAG tap: zynq.tap tap/device found: 0x13722093 (mfg: 0x049 (Xilinx), part: 0x3722, ver: 0x1) Warn : JTAG tap: zynq.tap UNEXPECTED: 0x13722093 (mfg: 0x049 (Xilinx), part: 0x3722, ver: 0x1) Error: JTAG tap: zynq.tap expected 1 of 1: 0x13723093 (mfg: 0x049 (Xilinx), part: 0x3723, ver: 0x1) Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) ```

astro commented

2020-01-24 07:16:46 +08:00

How? This is my Cora Z7-10:

Info : JTAG tap: zynq.tap tap/device found: 0x13723093 (mfg: 0x049 (Xilinx), part: 0x3723, ver: 0x1)
Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)

I think we can let the user provide overrides via the env. Ok?

How? This is my Cora Z7-**10**: ```text Info : JTAG tap: zynq.tap tap/device found: 0x13723093 (mfg: 0x049 (Xilinx), part: 0x3723, ver: 0x1) Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) ``` I think we can let the user provide overrides via the env. Ok?

sb10q commented

2020-04-17 14:33:13 +08:00

Poster

According to the BSDL files in Vivado:

attribute IDCODE_REGISTER of XC7Z010_CLG400 : entity is
	"XXXX" &	-- version
	"0011011" &	-- family
	"100100010" &	-- array size
	"00001001001" &	-- manufacturer
	"1";		-- required by 1149.1

attribute IDCODE_REGISTER of XC7Z007S_CLG400 : entity is
        "XXXX" &        -- version
        "0011011" &     -- family
        "100100011" &   -- array size
        "00001001001" & -- manufacturer
        "1";            -- required by 1149.1

So the values are supposed to be 0x13722093 for Z7-10 and 0x13723093 for Z7-07.

Are you sure your board has the correct chip?

According to the BSDL files in Vivado: ``` attribute IDCODE_REGISTER of XC7Z010_CLG400 : entity is "XXXX" & -- version "0011011" & -- family "100100010" & -- array size "00001001001" & -- manufacturer "1"; -- required by 1149.1 ``` ``` attribute IDCODE_REGISTER of XC7Z007S_CLG400 : entity is "XXXX" & -- version "0011011" & -- family "100100011" & -- array size "00001001001" & -- manufacturer "1"; -- required by 1149.1 ``` So the values are supposed to be 0x13722093 for Z7-10 and 0x13723093 for Z7-07. Are you sure your board has the correct chip?

astro commented

2020-05-14 09:29:06 +08:00

Embarrassing, I've got a -07.