some WIP exploration

Cargo.lock

@@ -1,10 +1,12 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
+version = 3
+
 [[package]]
 name = "bit_field"
-version = "0.10.1"
+version = "0.10.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
+checksum = "dc827186963e592360843fb5ba4b973e145841266c1357f7180c43526f2e5b61"
 
 [[package]]
 name = "bitflags"
@@ -13,37 +15,28 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
 
 [[package]]
-name = "byteorder"
+name = "bitflags"
-version = "1.4.3"
+version = "2.6.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
+checksum = "b048fb63fd8b5923fc5aa7b340d8e156aec7ec02f0c78fa8a6ddc2613f6f71de"
+
+[[package]]
+name = "byteorder"
+version = "1.5.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b"
 
 [[package]]
 name = "cc"
-version = "1.0.73"
+version = "1.1.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2fff2a6927b3bb87f9595d67196a70493f627687a71d87a0d692242c33f58c11"
+checksum = "26a5c3fd7bfa1ce3897a3a3501d362b2d87b7f2583ebcb4a949ec25911025cbc"
-
-[[package]]
-name = "cfg-if"
-version = "1.0.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "compiler_builtins"
-version = "0.1.39"
+version = "0.1.114"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
+checksum = "eb58b199190fcfe0846f55a3b545cd6b07a34bdd5930a476ff856f3ebcc5558a"
-
-[[package]]
-name = "core_io"
-version = "0.1.20210325"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
-dependencies = [
- "rustc_version",
-]
 
 [[package]]
 name = "embedded-hal"
@@ -70,13 +63,10 @@ dependencies = [
 
 [[package]]
 name = "fatfs"
-version = "0.3.5"
+version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
+source = "git+https://github.com/rafalh/rust-fatfs#85f06e08edbd3368e1b0562f2fc1b6d178bf7b8a"
-checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
 dependencies = [
- "bitflags",
+ "bitflags 2.6.0",
- "byteorder",
- "core_io",
  "log",
 ]
 
@@ -86,7 +76,7 @@ version = "0.0.0"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
- "nb 1.0.0",
+ "nb 1.1.0",
  "pin-utils",
  "smoltcp",
 ]
@@ -111,7 +101,6 @@ dependencies = [
 name = "libconfig"
 version = "0.1.0"
 dependencies = [
- "core_io",
  "fatfs",
  "libboard_zynq",
  "log",
@@ -156,12 +145,9 @@ checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
 
 [[package]]
 name = "log"
-version = "0.4.14"
+version = "0.4.22"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
+checksum = "a7a70ba024b9dc04c27ea2f0c0548feb474ec5c54bba33a7f72f873a39d07b24"
-dependencies = [
- "cfg-if",
-]
 
 [[package]]
 name = "managed"
@@ -175,14 +161,14 @@ version = "0.1.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f"
 dependencies = [
- "nb 1.0.0",
+ "nb 1.1.0",
 ]
 
 [[package]]
 name = "nb"
-version = "1.0.0"
+version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"
+checksum = "8d5439c4ad607c3c23abf66de8c8bf57ba8adcd1f129e699851a6e43935d339d"
 
 [[package]]
 name = "pin-utils"
@@ -196,28 +182,13 @@ version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "bd7a31eed1591dcbc95d92ad7161908e72f4677f8fabf2a32ca49b4237cbf211"
 
-[[package]]
-name = "rustc_version"
-version = "0.1.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
-dependencies = [
- "semver",
-]
-
-[[package]]
-name = "semver"
-version = "0.1.20"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
-
 [[package]]
 name = "smoltcp"
 version = "0.7.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "3e4a069bef843d170df47e7c0a8bf8d037f217d9f5b325865acc3e466ffe40d3"
 dependencies = [
- "bitflags",
+ "bitflags 1.3.2",
  "byteorder",
  "managed",
 ]
@@ -227,7 +198,6 @@ name = "szl"
 version = "0.1.0"
 dependencies = [
  "byteorder",
- "core_io",
  "libboard_zynq",
  "libconfig",
  "libcortex_a9",
@@ -250,9 +220,9 @@ checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
 
 [[package]]
 name = "volatile-register"
-version = "0.2.1"
+version = "0.2.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ee8f19f9d74293faf70901bc20ad067dc1ad390d2cbf1e3f75f721ffee908b6"
+checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
 dependencies = [
  "vcell",
 ]

experiments/src/main.rs

@@ -1,12 +1,11 @@
 #![no_std]
 #![no_main]
-#![feature(const_in_array_repeat_expressions)]
 #![feature(naked_functions)]
-#![feature(asm)]
 
 extern crate alloc;
 
 use alloc::collections::BTreeMap;
+use core::arch::asm;
 use libasync::{
     delay,
     smoltcp::{Sockets, TcpStream},

flake.lock

@@ -1,28 +1,12 @@
 {
   "nodes": {
-    "mozilla-overlay": {
-      "flake": false,
-      "locked": {
-        "lastModified": 1704373101,
-        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
-        "type": "github"
-      },
-      "original": {
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "type": "github"
-      }
-    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1720386169,
+        "lastModified": 1721548954,
-        "narHash": "sha256-NGKVY4PjzwAa4upkGtAMz1npHGoRzWotlSnVlqI40mo=",
+        "narHash": "sha256-7cCC8+Tdq1+3OPyc3+gVo9dzUNkNIQfwSDJ2HSi2u3o=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "194846768975b7ad2c4988bdb82572c00222c0d7",
+        "rev": "63d37ccd2d178d54e7fb691d7ec76000740ea24a",
         "type": "github"
       },
       "original": {
@@ -34,8 +18,28 @@
     },
     "root": {
       "inputs": {
-        "mozilla-overlay": "mozilla-overlay",
+        "nixpkgs": "nixpkgs",
-        "nixpkgs": "nixpkgs"
+        "rust-overlay": "rust-overlay"
+      }
+    },
+    "rust-overlay": {
+      "inputs": {
+        "nixpkgs": [
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1721701191,
+        "narHash": "sha256-nM4szL90VeZHZEC5rFfaiiPNTVOmsihdtk2QSP1l37I=",
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "rev": "4674ff2c2e5423a0cebe16e61aa874c359306af4",
+        "type": "github"
+      },
+      "original": {
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "type": "github"
       }
     }
   },

flake.nix

@@ -2,37 +2,47 @@
   description = "Bare-metal Rust on Zynq-7000";
 
   inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
-  inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
+  #inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };
+  inputs.rust-overlay = {
+    url = "github:oxalica/rust-overlay";
+    inputs.nixpkgs.follows = "nixpkgs";
+  };
 
-  outputs = { self, nixpkgs, mozilla-overlay }:
+  outputs = { self, nixpkgs, rust-overlay }:
     let
-      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) crosspkgs-overlay ]; };
+      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
       
-      rustManifest = pkgs.fetchurl {
+      # rustManifest = pkgs.fetchurl {
-        url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
+      #   url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
-        sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
+      #   sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
+      # };
+      # rustTargets = [];
+      # rustChannelOfTargets = _channel: _date: targets:
+      #   (pkgs.lib.rustLib.fromManifestFile rustManifest {
+      #     inherit (pkgs) stdenv lib fetchurl patchelf;
+      #     }).rust.override {
+      #     inherit targets;
+      #     extensions = ["rust-src"];
+      #   };
+      # rust = rustChannelOfTargets "nightly" null rustTargets;
+
+      # rustc version needs to match LLVM version, else ABI bugs
+      # https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
+      rust = pkgs.rust-bin.nightly."2023-04-20".default.override {
+        extensions = [ "rust-src" ];
       };
-      rustTargets = [];
-      rustChannelOfTargets = _channel: _date: targets:
-        (pkgs.lib.rustLib.fromManifestFile rustManifest {
-          inherit (pkgs) stdenv lib fetchurl patchelf;
-          }).rust.override {
-          inherit targets;
-          extensions = ["rust-src"];
-        };
-      rust = rustChannelOfTargets "nightly" null rustTargets;
       rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
         rustc = rust;
         cargo = rust;
       });
       
-      # https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
+      ## https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
-      llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
+      #llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
-        inherit (pkgs.stdenvAdapters) overrideCC;
+      #  inherit (pkgs.stdenvAdapters) overrideCC;
-        buildLlvmTools = null;
+      #  buildLlvmTools = null;
-        targetLlvmLibraries = null;
+      #  targetLlvmLibraries = null;
-        targetLlvm = null;
+      #  targetLlvm = null;
-      }));
+      #}));
 
       crosspkgs-overlay = (self: super: {
         pkgsCross = super.pkgsCross // {
@@ -104,9 +114,13 @@
         dontFixup = true;
       };
 
-      cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
+      cargo-xbuild = pkgs.cargo-xbuild;
-        postPatch = "substituteInPlace src/sysroot.rs --replace 2021 2018";
+      #cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
-      });
+      #  postPatch = "substituteInPlace src/sysroot.rs --replace 2021 2018";
+      #});
+      #cargo-xbuild = pkgs.cargo-xbuild.overrideAttrs(oa: {
+      #  postPatch = "substituteInPlace src/sysroot.rs --replace 2023 2018";
+      #});
 
       build-crate = name: crate: features: rustPlatform.buildRustPackage rec {
         name = "${crate}";
@@ -116,7 +130,7 @@
         ) ./.;
         cargoLock = { lockFile = ./Cargo.lock; };
 
-        nativeBuildInputs = [ cargo-xbuild llvmPackages_11.clang-unwrapped ];
+        nativeBuildInputs = [ cargo-xbuild pkgs.llvmPackages_16.clang-unwrapped ];
         buildPhase = ''
           export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
           export CARGO_HOME=$(mktemp -d cargo-home.XXX)
@@ -161,7 +175,7 @@
 
       hydraJobs = packages.x86_64-linux;
 
-      inherit rust rustPlatform llvmPackages_11;
+      inherit rust rustPlatform;
 
       devShell.x86_64-linux = pkgs.mkShell {
         name = "zynq-rs-dev-shell";
@@ -172,7 +186,7 @@
 
           pkgs.openocd pkgs.gdb
           pkgs.openssh pkgs.rsync
-          llvmPackages_11.clang-unwrapped
+          pkgs.llvmPackages_16.clang-unwrapped
           (pkgs.python3.withPackages(ps: [ ps.pyftdi ]))
         ];
       };

libconfig/Cargo.toml

@@ -6,8 +6,7 @@ edition = "2018"
 
 [dependencies]
 libboard_zynq = { path = "../libboard_zynq" }
-core_io = { version = "0.1", features = ["collections"] }
+fatfs = { default-features = false, git = "https://github.com/rafalh/rust-fatfs" }
-fatfs = { version = "0.3", features = ["core_io"], default-features = false }
 log = "0.4"
 
 [features]
@@ -16,4 +15,4 @@ target_coraz7 = []
 target_redpitaya = []
 target_kasli_soc = []
 ipv6 = []
-fat_lfn = [ "fatfs/alloc" ]
+fat_lfn = [ "fatfs/alloc" ]

libconfig/src/bootgen.rs

@@ -1,5 +1,7 @@
 use alloc::vec::Vec;
-use core_io::{Error, Read, Seek, SeekFrom};
+use fatfs::{Read, Seek, SeekFrom, IoBase};
+use core::fmt::Write;
+use crate::sd_reader::IoError;
 use libboard_zynq::devc;
 use log::debug;
 
@@ -8,12 +10,13 @@ pub enum BootgenLoadingError {
     InvalidBootImageHeader,
     MissingPartition,
     EncryptedBitstream,
-    IoError(Error),
+    IoError(IoError),
     DevcError(devc::DevcError),
 }
 
-impl From<Error> for BootgenLoadingError {
+
-    fn from(error: Error) -> Self {
+impl From<T: IoError> for BootgenLoadingError {
+    fn from(error: IoError) -> Self {
         BootgenLoadingError::IoError(error)
     }
 }
@@ -69,7 +72,7 @@ fn read_u32<Reader: Read>(reader: &mut Reader) -> Result<u32, BootgenLoadingErro
 }
 
 /// Load PL partition header.
-fn load_pl_header<File: Read + Seek>(
+fn load_pl_header<File: Read + Seek + IoBase>(
     file: &mut File,
 ) -> Result<Option<PartitionHeader>, BootgenLoadingError> {
     let mut buffer: [u8; 0x40] = [0; 0x40];

libconfig/src/lib.rs

@@ -3,7 +3,7 @@ extern crate alloc;
 
 use core::fmt;
 use alloc::{string::FromUtf8Error, string::String, vec::Vec, rc::Rc};
-use core_io::{self as io, BufRead, BufReader, Read, Write, Seek, SeekFrom};
+use fatfs::{self as fatfs, SeekFrom, Write, Read, Seek};
 use libboard_zynq::sdio;
 
 pub mod sd_reader;
@@ -13,7 +13,7 @@ pub mod bootgen;
 #[derive(Debug)]
 pub enum Error<'a> {
     SdError(sdio::sd_card::CardInitializationError),
-    IoError(io::Error),
+    IoError(fatfs::Error<sd_reader::IoError>),
     Utf8Error(FromUtf8Error),
     KeyNotFoundError(&'a str),
     NoConfig,
@@ -39,8 +39,8 @@ impl<'a> From<sdio::sd_card::CardInitializationError> for Error<'a> {
     }
 }
 
-impl<'a> From<io::Error> for Error<'a> {
+impl<'a> From<fatfs::Error<sd_reader::IoError>> for Error<'a> {
-    fn from(error: io::Error) -> Self {
+    fn from(error: fatfs::Error<sd_reader::IoError>) -> Self {
         Error::IoError(error)
     }
 }
@@ -51,14 +51,19 @@ impl<'a> From<FromUtf8Error> for Error<'a> {
     }
 }
 
+pub type FFile = fatfs::File<sd_reader::SdReader, fatfs::DefaultTimeProvider, fatfs::LossyOemCpConverter>;
+
 fn parse_config<'a>(
     key: &'a str,
     buffer: &mut Vec<u8>,
-    file: fatfs::File<sd_reader::SdReader>,
+    file: FFile,
 ) -> Result<'a, ()> {
     let prefix = [key, "="].concat().to_ascii_lowercase();
-    for line in BufReader::new(file).lines() {
+    let file_buf = &mut []; 
-        let line = line?.to_ascii_lowercase();
+    let length = file.read(file_buf)?;
+    let s = core::str::from_utf8(file_buf)?;
+    for line in s.lines() {
+        let line = line.make_ascii_lowercase()?;
         if line.starts_with(&prefix) {
             buffer.extend(line[prefix.len()..].as_bytes());
             return Ok(());

libconfig/src/sd_reader.rs

@@ -1,8 +1,8 @@
-use core_io::{BufRead, Error, ErrorKind, Read, Result as IoResult, Seek, SeekFrom, Write};
+use fatfs::{self as fatfs, Read, Seek, SeekFrom, Write, IoBase, IoError as BaseIoError};
-use fatfs;
 use libboard_zynq::sdio::{sd_card::SdCard, CmdTransferError};
 use log::debug;
 use alloc::vec::Vec;
+use alloc::string::String;
 
 const MBR_SIGNATURE: [u8; 2] = [0x55, 0xAA];
 const PARTID_FAT12: u8 = 0x01;
@@ -12,12 +12,49 @@ const PARTID_FAT32: u8 = 0x0B;
 const PARTID_FAT32_LBA: u8 = 0x0C;
 const PARTID_FAT16_LBA: u8 = 0x0E;
 
-fn cmd_error_to_io_error(_: CmdTransferError) -> Error {
-    Error::new(ErrorKind::Other, "Command transfer error")
-}
 
 const BLOCK_SIZE: usize = 512;
 
+#[derive(Debug)]
+pub enum ErrorKind {
+    InvalidData,
+    InvalidInput,
+    Other
+}
+
+#[derive(Debug)]
+pub struct IoError {
+    error: ErrorKind,
+    message: String
+}
+
+impl IoError {
+    pub fn new(error: ErrorKind, message: &str) -> Self {
+       IoError {
+            error,
+            message: String::from(message)
+       }
+    }
+}
+
+impl BaseIoError for IoError {
+    fn is_interrupted() -> IoError {
+        false
+    }
+    fn new_unexpected_eof_error() -> IoError{
+        
+    }
+    fn new_write_zero_error() -> IoError {
+
+    }
+}
+
+pub type IoResult<T> = core::Result<T, IoError>;
+
+fn cmd_error_to_io_error(_: CmdTransferError) -> IoError {
+    IoError::new(ErrorKind::Other, "Command transfer error")
+}
+
 /// SdReader struct implementing `Read + BufRead + Write + Seek` traits for `core_io`.
 /// Used as an adaptor for fatfs crate, but could be used directly for raw data access.
 ///
@@ -53,6 +90,10 @@ pub enum PartitionEntry {
     Entry4 = 0x1EE,
 }
 
+impl IoBase for SdReader {
+    type Error = IoError;
+}
+
 impl SdReader {
     /// Create SdReader from SdCard
     pub fn new(sd: SdCard) -> SdReader {
@@ -151,10 +192,7 @@ impl SdReader {
         self.read_exact(&mut buffer[..2])?;
         // check MBR signature
         if buffer[..2] != MBR_SIGNATURE {
-            return Err(Error::new(
+            return Err(IoError::new(ErrorKind::InvalidData, "Incorrect signature for MBR sector."));
-                ErrorKind::InvalidData,
-                "Incorrect signature for MBR sector.",
-            ));
         }
         // Read partition ID.
         self.seek(SeekFrom::Start(entry as u64 + 0x4))?;
@@ -164,9 +202,8 @@ impl SdReader {
             PARTID_FAT12 | PARTID_FAT16_LESS32M | PARTID_FAT16 |
             PARTID_FAT16_LBA | PARTID_FAT32 | PARTID_FAT32_LBA => {}
             _ => {
-                return Err(Error::new(
+                return Err(IoError::new(ErrorKind::InvalidData, 
-                    ErrorKind::InvalidData,
+                    "No FAT partition found for the specified entry."
-                    "No FAT partition found for the specified entry.",
                 ));
             }
         }
@@ -183,8 +220,29 @@ impl SdReader {
         // setup fatfs
         fatfs::FileSystem::new(self, fatfs::FsOptions::new())
     }
+
+     fn fill_buf(&mut self) -> IoResult<&[u8]> {
+         if self.index == BLOCK_SIZE {
+             // flush the buffer if it is dirty before overwriting it with new data
+             if self.dirty {
+                 self.flush()?;
+             }
+             // reload buffer
+             self.sd
+                 .read_block(self.byte_addr / (BLOCK_SIZE as u32), 1, &mut self.buffer)
+                 .map_err(cmd_error_to_io_error)?;
+             self.index = (self.byte_addr as usize) % BLOCK_SIZE;
+         }
+         Ok(&self.buffer[self.index..])
+     }
+ 
+     fn consume(&mut self, amt: usize) {
+         self.index += amt;
+         self.byte_addr += amt as u32;
+     }
 }
 
+
 impl Read for SdReader {
     fn read(&mut self, buf: &mut [u8]) -> IoResult<usize> {
         let total_length = buf.len();
@@ -211,28 +269,6 @@ impl Read for SdReader {
     }
 }
 
-impl BufRead for SdReader {
-    fn fill_buf(&mut self) -> IoResult<&[u8]> {
-        if self.index == BLOCK_SIZE {
-            // flush the buffer if it is dirty before overwriting it with new data
-            if self.dirty {
-                self.flush()?;
-            }
-            // reload buffer
-            self.sd
-                .read_block(self.byte_addr / (BLOCK_SIZE as u32), 1, &mut self.buffer)
-                .map_err(cmd_error_to_io_error)?;
-            self.index = (self.byte_addr as usize) % BLOCK_SIZE;
-        }
-        Ok(&self.buffer[self.index..])
-    }
-
-    fn consume(&mut self, amt: usize) {
-        self.index += amt;
-        self.byte_addr += amt as u32;
-    }
-}
-
 impl Write for SdReader {
     fn write(&mut self, buf: &[u8]) -> IoResult<usize> {
         let (a, b, c) = self.block_align(buf);
@@ -260,7 +296,7 @@ impl Write for SdReader {
             let block_addr = (self.byte_addr - self.index as u32) / (BLOCK_SIZE as u32);
             self.sd
                 .write_block(block_addr, 1, &self.buffer)
-                .map_err(cmd_error_to_io_error)?;
+                .map_err(self.cmd_error_to_io_error)?;
             self.dirty = false;
         }
         Ok(())
@@ -275,7 +311,7 @@ impl Seek for SdReader {
             SeekFrom::End(_) => panic!("SD card does not support seek from end"),
         };
         if raw_target < self.offset as i64 || raw_target > core::u32::MAX as i64 {
-            return Err(Error::new(ErrorKind::InvalidInput, "Invalid address"));
+            return Err(IoError::new(ErrorKind::InvalidInput, "Invalid address"));
         }
         let target_byte_addr = raw_target as u32;
         let address_same_block =

libcortex_a9/src/asm.rs

@@ -1,59 +1,60 @@
+use core::arch::asm;
+
 /// The classic no-op
 #[inline]
 pub fn nop() {
-    unsafe { llvm_asm!("nop" :::: "volatile") }
+    unsafe { asm!("nop") }
 }
 
 /// Wait For Event
 #[inline]
 pub fn wfe() {
-    unsafe { llvm_asm!("wfe" :::: "volatile") }
+    unsafe { asm!("wfe") }
 }
 
 /// Send Event
 #[inline]
 pub fn sev() {
-    unsafe { llvm_asm!("sev" :::: "volatile") }
+    unsafe { asm!("sev") }
 }
 
 /// Data Memory Barrier
 #[inline]
 pub fn dmb() {
-    unsafe { llvm_asm!("dmb" :::: "volatile") }
+    unsafe { asm!("dmb") }
 }
 
 /// Data Synchronization Barrier
 #[inline]
 pub fn dsb() {
-    unsafe { llvm_asm!("dsb" :::: "volatile") }
+    unsafe { asm!("dsb") }
 }
 
 /// Instruction Synchronization Barrier
 #[inline]
 pub fn isb() {
-    unsafe { llvm_asm!("isb" :::: "volatile") }
+    unsafe { asm!("isb") }
 }
 
 /// Enable FIQ
 #[inline]
 pub unsafe fn enable_fiq() {
-    llvm_asm!("cpsie f":::: "volatile");
+    asm!("cpsie f");
 }
 
 /// Enable IRQ
 #[inline]
 pub unsafe fn enable_irq() {
-    llvm_asm!("cpsie i":::: "volatile");
+    asm!("cpsie i");
 }
 
 /// Disable IRQ, return if IRQ was originally enabled.
 #[inline]
 pub unsafe fn enter_critical() -> bool {
     let mut cpsr: u32;
-    llvm_asm!(
+    asm!(
-        "mrs $0, cpsr
+        "mrs {}, cpsr
-         cpsid i"
+         cpsid i", out(reg) cpsr);
-         : "=r"(cpsr) ::: "volatile");
     (cpsr & (1 << 7)) == 0
 }
 
@@ -65,18 +66,18 @@ pub unsafe fn exit_critical(enable: bool) {
     } else {
         0
     };
-    llvm_asm!(
+    asm!(
         "mrs r1, cpsr
-         bic r1, r1, $0
+         bic r1, r1, {}
          msr cpsr_c, r1"
-         :: "r"(mask) : "r1");
+         , in(reg) mask);
 }
 
 /// Exiting IRQ
 #[inline]
 pub unsafe fn exit_irq() {
-    llvm_asm!("
+    asm!("
         mrs r0, SPSR
         msr CPSR, r0
-        " ::: "r0");
+        ");
 }

libcortex_a9/src/cache.rs

@@ -1,11 +1,12 @@
 use super::asm::{dmb, dsb};
 use super::l2c::*;
+use core::arch::asm;
 
 /// Invalidate TLBs
 #[inline(always)]
 pub fn tlbiall() {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 0, {}, c8, c7, 0", in(reg) 0);
     }
 }
 
@@ -13,7 +14,7 @@ pub fn tlbiall() {
 #[inline(always)]
 pub fn iciallu() {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c5, 0", in(reg) 0);
     }
 }
 
@@ -21,7 +22,7 @@ pub fn iciallu() {
 #[inline(always)]
 pub fn bpiall() {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c5, 6", in(reg) 0);
     }
 }
 
@@ -29,7 +30,7 @@ pub fn bpiall() {
 #[inline(always)]
 pub fn dccsw(setway: u32) {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c10, 2", in(reg) setway);
     }
 }
 
@@ -41,7 +42,7 @@ pub fn dcisw(setway: u32) {
         // also see example code (for DCCISW, but DCISW will be
         // analogous) "Example code for cache maintenance operations"
         // on pages B2-1286 and B2-1287.
-        llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c6, 2", in(reg) setway);
     }
 }
 
@@ -49,7 +50,7 @@ pub fn dcisw(setway: u32) {
 #[inline(always)]
 pub fn dccisw(setway: u32) {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c14, 2", in(reg) setway);
     }
 }
 
@@ -69,7 +70,7 @@ pub fn dciall_l1() {
 
     // select L1 data cache
     unsafe {
-        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
     }
 
     // Invalidate entire D-Cache by iterating every set and every way
@@ -104,7 +105,7 @@ pub fn dcciall_l1() {
 
     // select L1 data cache
     unsafe {
-        llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
+        asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
     }
 
     // Invalidate entire D-Cache by iterating every set and every way
@@ -156,7 +157,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
 #[inline(always)]
 pub fn dccimvac(addr: usize) {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c14, 1", in(reg) addr);
     }
 }
 
@@ -198,10 +199,9 @@ pub fn dcci_slice<T>(slice: &[T]) {
 #[inline(always)]
 pub fn dccmvac(addr: usize) {
     unsafe {
-        llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
+        asm!("mcr p15, 0, {}, c7, c10, 1", in(reg) addr);
     }
 }
-
 /// Data cache clean for an object.
 pub fn dcc<T>(object: &T) {
     dmb();
@@ -239,7 +239,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
 /// affecting more data than intended.
 #[inline(always)]
 pub unsafe fn dcimvac(addr: usize) {
-    llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
+    asm!("mcr p15, 0, {}, c7, c6, 1", in(reg) addr);
 }
 
 /// Data cache clean and invalidate for an object.

libcortex_a9/src/fpu.rs

@@ -1,7 +1,8 @@
+use core::arch::asm;
 /// Enable FPU in the current core.
 pub fn enable_fpu() {
     unsafe {
-        llvm_asm!("
+        asm!("
             mrc p15, 0, r1, c1, c0, 2
             orr r1, r1, (0b1111<<20)
             mcr p15, 0, r1, c1, c0, 2
@@ -9,6 +10,6 @@ pub fn enable_fpu() {
             vmrs r1, fpexc
             orr r1, r1, (1<<30)
             vmsr fpexc, r1
-            ":::"r1");
+            ");
     }
 }

libcortex_a9/src/lib.rs

@@ -1,7 +1,5 @@
 #![no_std]
-#![feature(llvm_asm, global_asm)]
 #![feature(never_type)]
-#![feature(const_fn)]
 
 extern crate alloc;
 
@@ -17,6 +15,7 @@ pub mod sync_channel;
 mod uncached;
 pub use fpu::enable_fpu;
 pub use uncached::UncachedSlice;
+use core::arch::global_asm;
 
 global_asm!(include_str!("exceptions.s"));
 

libcortex_a9/src/regs.rs

@@ -2,6 +2,7 @@ use libregister::{
     register_bit, register_bits,
     RegisterR, RegisterW, RegisterRW,
 };
+use core::arch::asm;
 
 macro_rules! def_reg_r {
     ($name:tt, $type: ty, $asm_instr:tt) => {
@@ -11,7 +12,7 @@ macro_rules! def_reg_r {
             #[inline]
             fn read(&self) -> Self::R {
                 let mut value: u32;
-                unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
+                unsafe { asm!($asm_instr, out(reg) value) }
                 value.into()
             }
         }
@@ -26,7 +27,7 @@ macro_rules! def_reg_w {
             #[inline]
             fn write(&mut self, value: Self::W) {
                 let value: u32 = value.into();
-                unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
+                unsafe { asm!($asm_instr, in(reg) value) }
             }
 
             #[inline]
@@ -71,29 +72,29 @@ macro_rules! wrap_reg {
 
 /// Stack Pointer
 pub struct SP;
-def_reg_r!(SP, u32, "mov $0, sp");
+def_reg_r!(SP, u32, "mov {}, sp");
-def_reg_w!(SP, u32, "mov sp, $0");
+def_reg_w!(SP, u32, "mov sp, {}");
 
 /// Link register (function call return address)
 pub struct LR;
-def_reg_r!(LR, u32, "mov $0, lr");
+def_reg_r!(LR, u32, "mov {}, lr");
-def_reg_w!(LR, u32, "mov lr, $0");
+def_reg_w!(LR, u32, "mov lr, {}");
 
 pub struct VBAR;
-def_reg_r!(VBAR, u32, "mrc p15, 0, $0, c12, c0, 0");
+def_reg_r!(VBAR, u32, "mrc p15, 0, {}, c12, c0, 0");
-def_reg_w!(VBAR, u32, "mcr p15, 0, $0, c12, c0, 0");
+def_reg_w!(VBAR, u32, "mcr p15, 0, {}, c12, c0, 0");
 
 pub struct MVBAR;
-def_reg_r!(MVBAR, u32, "mrc p15, 0, $0, c12, c0, 1");
+def_reg_r!(MVBAR, u32, "mrc p15, 0, {}, c12, c0, 1");
-def_reg_w!(MVBAR, u32, "mcr p15, 0, $0, c12, c0, 1");
+def_reg_w!(MVBAR, u32, "mcr p15, 0, {}, c12, c0, 1");
 
 pub struct HVBAR;
-def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
+def_reg_r!(HVBAR, u32, "mrc p15, 4, {}, c12, c0, 0");
-def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
+def_reg_w!(HVBAR, u32, "mcr p15, 4, {}, c12, c0, 0");
 
 /// Multiprocess Affinity Register
 pub struct MPIDR;
-def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
+def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, {}, c0, c0, 5");
 wrap_reg!(mpidr);
 register_bits!(mpidr,
                /// CPU core index
@@ -106,15 +107,15 @@ register_bit!(mpidr,
               u, 30);
 
 pub struct DFAR;
-def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
+def_reg_r!(DFAR, u32, "mrc p15, 0, {}, c6, c0, 0");
 
 pub struct DFSR;
-def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
+def_reg_r!(DFSR, u32, "mrc p15, 0, {}, c5, c0, 0");
 
 pub struct SCTLR;
 wrap_reg!(sctlr);
-def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
+def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, {}, c1, c0, 0");
-def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
+def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, {}, c1, c0, 0");
 register_bit!(sctlr,
               /// Enables MMU
               m, 0);
@@ -147,8 +148,8 @@ register_bit!(sctlr,
 /// Auxiliary Control Register
 pub struct ACTLR;
 wrap_reg!(actlr);
-def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
+def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, {}, c1, c0, 1");
-def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
+def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, {}, c1, c0, 1");
 // SMP bit
 register_bit!(actlr, parity_on, 9);
 register_bit!(actlr, alloc_one_way, 8);
@@ -183,17 +184,17 @@ impl ACTLR {
 
 /// Domain Access Control Register
 pub struct DACR;
-def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
+def_reg_r!(DACR, u32, "mrc p15, 0, {}, c3, c0, 0");
-def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
+def_reg_w!(DACR, u32, "mcr p15, 0, {}, c3, c0, 0");
 
 /// Translation Table Base Register 0
 pub struct TTBR0;
 /// Translation Table Base Register 1
 pub struct TTBR1;
-def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
+def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, {}, c2, c0, 0");
-def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
+def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, {}, c2, c0, 0");
-def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
+def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, {}, c2, c0, 1");
-def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
+def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, {}, c2, c0, 1");
 wrap_reg!(ttbr);
 register_bits!(ttbr, table_base, u32, 14, 31);
 register_bit!(ttbr, irgn0, 6);

libcortex_a9/src/sync_channel.rs

@@ -178,7 +178,8 @@ macro_rules! sync_channel {
         {
             use core::sync::atomic::{AtomicUsize, AtomicPtr};
             use $crate::sync_channel::{Sender, Receiver};
-            static LIST: [AtomicPtr<$t>; $cap + 1] = [AtomicPtr::new(core::ptr::null_mut()); $cap + 1];
+            const cnst_ptr: AtomicPtr<$t> = AtomicPtr::new(core::ptr::null_mut());
+            static LIST: [AtomicPtr<$t>; $cap + 1] = [cnst_ptr; $cap + 1];
             static WRITE: AtomicUsize = AtomicUsize::new(0);
             static READ: AtomicUsize = AtomicUsize::new(0);
             (Sender::new(&LIST, &WRITE, &READ), Receiver::new(&LIST, &WRITE, &READ))

libsupport_zynq/Cargo.toml

@@ -19,7 +19,7 @@ default = ["panic_handler", "dummy_irq_handler", "dummy_fiq_handler"]
 
 [dependencies]
 r0 = "1"
-compiler_builtins = "=0.1.39"
+compiler_builtins = { version = "0.1", features = ["no-f16-f128"] }
 linked_list_allocator = { version = "0.8", default-features = false, features = ["const_mut_refs"] }
 libregister = { path = "../libregister" }
 libcortex_a9 = { path = "../libcortex_a9" }

libsupport_zynq/src/boot.rs

@@ -1,5 +1,6 @@
 use r0::zero_bss;
 use core::ptr::write_volatile;
+use core::arch::asm;
 use libregister::{
     VolatileCell,
     RegisterR, RegisterRW,

libsupport_zynq/src/exception_vectors.rs

@@ -1,6 +1,7 @@
 use libregister::{RegisterR, RegisterW};
 use libcortex_a9::{regs::{DFSR, MPIDR, VBAR}, interrupt_handler};
 use libboard_zynq::{println, stdio}; 
+use core::arch::asm;
 
 pub fn set_vector_table(base_addr: u32){
     VBAR.write(base_addr);

libsupport_zynq/src/lib.rs

@@ -3,7 +3,6 @@
 #![feature(alloc_error_handler)]
 #![feature(panic_info_message)]
 #![feature(naked_functions)]
-#![feature(asm)]
 
 pub extern crate alloc;
 pub extern crate compiler_builtins;

szl/Cargo.toml

@@ -15,7 +15,6 @@ default = ["target_zc706"]
 [dependencies]
 log = "0.4"
 byteorder = { version = "1.3", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
 
 libboard_zynq = { path = "../libboard_zynq" }
 libsupport_zynq = { path = "../libsupport_zynq" }