forked from M-Labs/zynq-rs
llvm_asm to asm macro
This commit is contained in:
parent
85dc1cc258
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7c09846855
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@ -1,11 +1,11 @@
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#![no_std]
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#![no_main]
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#![feature(naked_functions)]
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#![feature(asm)]
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extern crate alloc;
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use alloc::collections::BTreeMap;
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use core::arch::asm;
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use libasync::{
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delay,
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smoltcp::{Sockets, TcpStream},
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@ -1,59 +1,60 @@
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use core::arch::asm;
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/// The classic no-op
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#[inline]
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pub fn nop() {
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unsafe { llvm_asm!("nop" :::: "volatile") }
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unsafe { asm!("nop") }
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}
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/// Wait For Event
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#[inline]
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pub fn wfe() {
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unsafe { llvm_asm!("wfe" :::: "volatile") }
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unsafe { asm!("wfe") }
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}
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/// Send Event
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#[inline]
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pub fn sev() {
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unsafe { llvm_asm!("sev" :::: "volatile") }
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unsafe { asm!("sev") }
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}
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/// Data Memory Barrier
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#[inline]
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pub fn dmb() {
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unsafe { llvm_asm!("dmb" :::: "volatile") }
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unsafe { asm!("dmb") }
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}
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/// Data Synchronization Barrier
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#[inline]
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pub fn dsb() {
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unsafe { llvm_asm!("dsb" :::: "volatile") }
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unsafe { asm!("dsb") }
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}
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/// Instruction Synchronization Barrier
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#[inline]
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pub fn isb() {
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unsafe { llvm_asm!("isb" :::: "volatile") }
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unsafe { asm!("isb") }
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}
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/// Enable FIQ
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#[inline]
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pub unsafe fn enable_fiq() {
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llvm_asm!("cpsie f":::: "volatile");
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asm!("cpsie f");
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}
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/// Enable IRQ
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#[inline]
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pub unsafe fn enable_irq() {
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llvm_asm!("cpsie i":::: "volatile");
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asm!("cpsie i");
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}
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/// Disable IRQ, return if IRQ was originally enabled.
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#[inline]
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pub unsafe fn enter_critical() -> bool {
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let mut cpsr: u32;
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llvm_asm!(
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"mrs $0, cpsr
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cpsid i"
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: "=r"(cpsr) ::: "volatile");
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asm!(
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"mrs {}, cpsr
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cpsid i", out(reg) cpsr);
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(cpsr & (1 << 7)) == 0
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}
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@ -65,18 +66,18 @@ pub unsafe fn exit_critical(enable: bool) {
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} else {
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0
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};
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llvm_asm!(
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asm!(
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"mrs r1, cpsr
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bic r1, r1, $0
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bic r1, r1, {}
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msr cpsr_c, r1"
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:: "r"(mask) : "r1");
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, in(reg) mask);
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}
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/// Exiting IRQ
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#[inline]
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pub unsafe fn exit_irq() {
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llvm_asm!("
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asm!("
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mrs r0, SPSR
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msr CPSR, r0
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" ::: "r0");
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");
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}
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@ -1,11 +1,12 @@
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use super::asm::{dmb, dsb};
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use super::l2c::*;
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use core::arch::asm;
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/// Invalidate TLBs
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#[inline(always)]
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pub fn tlbiall() {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
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asm!("mcr p15, 0, {}, c8, c7, 0", in(reg) 0);
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}
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}
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@ -13,7 +14,7 @@ pub fn tlbiall() {
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#[inline(always)]
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pub fn iciallu() {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c5, 0", in(reg) 0);
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}
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}
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@ -21,7 +22,7 @@ pub fn iciallu() {
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#[inline(always)]
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pub fn bpiall() {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c5, 6", in(reg) 0);
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}
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}
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@ -29,7 +30,7 @@ pub fn bpiall() {
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#[inline(always)]
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pub fn dccsw(setway: u32) {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c10, 2", in(reg) setway);
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}
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}
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@ -41,7 +42,7 @@ pub fn dcisw(setway: u32) {
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// also see example code (for DCCISW, but DCISW will be
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// analogous) "Example code for cache maintenance operations"
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// on pages B2-1286 and B2-1287.
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llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c6, 2", in(reg) setway);
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}
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}
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@ -49,7 +50,7 @@ pub fn dcisw(setway: u32) {
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#[inline(always)]
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pub fn dccisw(setway: u32) {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c14, 2" :: "r" (setway) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c14, 2", in(reg) setway);
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}
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}
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@ -69,7 +70,7 @@ pub fn dciall_l1() {
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// select L1 data cache
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unsafe {
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llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
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asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
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}
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// Invalidate entire D-Cache by iterating every set and every way
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@ -104,7 +105,7 @@ pub fn dcciall_l1() {
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// select L1 data cache
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unsafe {
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llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
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asm!("mcr p15, 2, {}, c0, c0, 0", in(reg) 0);
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}
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// Invalidate entire D-Cache by iterating every set and every way
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@ -156,7 +157,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
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#[inline(always)]
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pub fn dccimvac(addr: usize) {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c14, 1", in(reg) addr);
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}
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}
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@ -198,10 +199,9 @@ pub fn dcci_slice<T>(slice: &[T]) {
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#[inline(always)]
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pub fn dccmvac(addr: usize) {
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unsafe {
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llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c10, 1", in(reg) addr);
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}
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}
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/// Data cache clean for an object.
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pub fn dcc<T>(object: &T) {
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dmb();
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@ -239,7 +239,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
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/// affecting more data than intended.
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#[inline(always)]
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pub unsafe fn dcimvac(addr: usize) {
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llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
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asm!("mcr p15, 0, {}, c7, c6, 1", in(reg) addr);
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}
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/// Data cache clean and invalidate for an object.
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use core::arch::asm;
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/// Enable FPU in the current core.
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pub fn enable_fpu() {
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unsafe {
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llvm_asm!("
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asm!("
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mrc p15, 0, r1, c1, c0, 2
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orr r1, r1, (0b1111<<20)
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mcr p15, 0, r1, c1, c0, 2
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vmrs r1, fpexc
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orr r1, r1, (1<<30)
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vmsr fpexc, r1
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":::"r1");
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");
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}
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}
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#![no_std]
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#![feature(llvm_asm, global_asm)]
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#![feature(never_type)]
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#![feature(const_fn_trait_bound)]
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extern crate alloc;
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mod uncached;
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pub use fpu::enable_fpu;
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pub use uncached::UncachedSlice;
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use core::arch::global_asm;
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global_asm!(include_str!("exceptions.s"));
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@ -2,6 +2,7 @@ use libregister::{
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register_bit, register_bits,
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RegisterR, RegisterW, RegisterRW,
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};
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use core::arch::asm;
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macro_rules! def_reg_r {
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($name:tt, $type: ty, $asm_instr:tt) => {
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#[inline]
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fn read(&self) -> Self::R {
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let mut value: u32;
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unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
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unsafe { asm!($asm_instr, out(reg) value) }
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value.into()
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}
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}
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#[inline]
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fn write(&mut self, value: Self::W) {
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let value: u32 = value.into();
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unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
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unsafe { asm!($asm_instr, in(reg) value) }
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}
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#[inline]
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/// Stack Pointer
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pub struct SP;
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def_reg_r!(SP, u32, "mov $0, sp");
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def_reg_w!(SP, u32, "mov sp, $0");
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def_reg_r!(SP, u32, "mov {}, sp");
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def_reg_w!(SP, u32, "mov sp, {}");
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/// Link register (function call return address)
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pub struct LR;
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def_reg_r!(LR, u32, "mov $0, lr");
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def_reg_w!(LR, u32, "mov lr, $0");
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def_reg_r!(LR, u32, "mov {}, lr");
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def_reg_w!(LR, u32, "mov lr, {}");
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pub struct VBAR;
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def_reg_r!(VBAR, u32, "mrc p15, 0, $0, c12, c0, 0");
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def_reg_w!(VBAR, u32, "mcr p15, 0, $0, c12, c0, 0");
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def_reg_r!(VBAR, u32, "mrc p15, 0, {}, c12, c0, 0");
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def_reg_w!(VBAR, u32, "mcr p15, 0, {}, c12, c0, 0");
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pub struct MVBAR;
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def_reg_r!(MVBAR, u32, "mrc p15, 0, $0, c12, c0, 1");
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def_reg_w!(MVBAR, u32, "mcr p15, 0, $0, c12, c0, 1");
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def_reg_r!(MVBAR, u32, "mrc p15, 0, {}, c12, c0, 1");
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def_reg_w!(MVBAR, u32, "mcr p15, 0, {}, c12, c0, 1");
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pub struct HVBAR;
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def_reg_r!(HVBAR, u32, "mrc p15, 4, $0, c12, c0, 0");
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def_reg_w!(HVBAR, u32, "mcr p15, 4, $0, c12, c0, 0");
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def_reg_r!(HVBAR, u32, "mrc p15, 4, {}, c12, c0, 0");
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def_reg_w!(HVBAR, u32, "mcr p15, 4, {}, c12, c0, 0");
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/// Multiprocess Affinity Register
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pub struct MPIDR;
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def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
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def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, {}, c0, c0, 5");
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wrap_reg!(mpidr);
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register_bits!(mpidr,
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/// CPU core index
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@ -106,15 +107,15 @@ register_bit!(mpidr,
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u, 30);
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pub struct DFAR;
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def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
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def_reg_r!(DFAR, u32, "mrc p15, 0, {}, c6, c0, 0");
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pub struct DFSR;
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def_reg_r!(DFSR, u32, "mrc p15, 0, $0, c5, c0, 0");
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def_reg_r!(DFSR, u32, "mrc p15, 0, {}, c5, c0, 0");
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pub struct SCTLR;
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wrap_reg!(sctlr);
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def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
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def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, $0, c1, c0, 0");
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def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, {}, c1, c0, 0");
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def_reg_w!(SCTLR, sctlr::Write, "mcr p15, 0, {}, c1, c0, 0");
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register_bit!(sctlr,
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/// Enables MMU
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m, 0);
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@ -147,8 +148,8 @@ register_bit!(sctlr,
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/// Auxiliary Control Register
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pub struct ACTLR;
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wrap_reg!(actlr);
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def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
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def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
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def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, {}, c1, c0, 1");
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def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, {}, c1, c0, 1");
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// SMP bit
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register_bit!(actlr, parity_on, 9);
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register_bit!(actlr, alloc_one_way, 8);
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@ -183,17 +184,17 @@ impl ACTLR {
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/// Domain Access Control Register
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pub struct DACR;
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def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
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def_reg_w!(DACR, u32, "mcr p15, 0, $0, c3, c0, 0");
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def_reg_r!(DACR, u32, "mrc p15, 0, {}, c3, c0, 0");
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def_reg_w!(DACR, u32, "mcr p15, 0, {}, c3, c0, 0");
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/// Translation Table Base Register 0
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pub struct TTBR0;
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/// Translation Table Base Register 1
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pub struct TTBR1;
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def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, $0, c2, c0, 0");
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def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, $0, c2, c0, 0");
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def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, $0, c2, c0, 1");
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def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, $0, c2, c0, 1");
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def_reg_r!(TTBR0, ttbr::Read, "mrc p15, 0, {}, c2, c0, 0");
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def_reg_w!(TTBR0, ttbr::Write, "mcr p15, 0, {}, c2, c0, 0");
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def_reg_r!(TTBR1, ttbr::Read, "mrc p15, 0, {}, c2, c0, 1");
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def_reg_w!(TTBR1, ttbr::Write, "mcr p15, 0, {}, c2, c0, 1");
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wrap_reg!(ttbr);
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register_bits!(ttbr, table_base, u32, 14, 31);
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register_bit!(ttbr, irgn0, 6);
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@ -1,5 +1,6 @@
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use r0::zero_bss;
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use core::ptr::write_volatile;
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use core::arch::asm;
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use libregister::{
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VolatileCell,
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RegisterR, RegisterRW,
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@ -1,6 +1,7 @@
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use libregister::{RegisterR, RegisterW};
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use libcortex_a9::{regs::{DFSR, MPIDR, VBAR}, interrupt_handler};
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use libboard_zynq::{println, stdio};
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use core::arch::asm;
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pub fn set_vector_table(base_addr: u32){
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VBAR.write(base_addr);
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@ -3,7 +3,6 @@
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#![feature(alloc_error_handler)]
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#![feature(panic_info_message)]
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#![feature(naked_functions)]
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#![feature(asm)]
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pub extern crate alloc;
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pub extern crate compiler_builtins;
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