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1 Commits
Author | SHA1 | Date | |
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8f9b8a7f3d |
@ -3,7 +3,10 @@
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use core::mem::transmute;
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use libcortex_a9::mutex::Mutex;
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use libboard_zynq::{print, println, self as zynq};
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use libboard_zynq::{print, println, self as zynq,
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dmac::{DmaC},
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devc::{DevC},
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};
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use libboard_zc706::{
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ram, alloc::{vec, vec::Vec},
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boot,
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@ -13,6 +16,8 @@ use libboard_zc706::{
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smoltcp::socket::SocketSet,
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smoltcp::socket::{TcpSocket, TcpSocketBuffer},
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};
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mod pl_config;
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use pl_config::load_pl;
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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@ -20,6 +25,8 @@ static mut STACK_CORE1: [u32; 512] = [0; 512];
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#[no_mangle]
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pub fn main_core0() {
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let mut devc = DevC::new();
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load_pl(&mut devc);
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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{
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17
experiments/src/pl_config.rs
Normal file
17
experiments/src/pl_config.rs
Normal file
@ -0,0 +1,17 @@
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use libboard_zynq::{print, println, self as zynq,
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devc::{DevC},
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};
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pub fn load_pl(devc: &mut DevC) {
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devc.enable_and_select_pcap();
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devc.clear_interrupts(); // removed despite TRM suggestion
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devc.initialize_pl();
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devc.wait_for_pl_to_be_ready();
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devc.wait_for_command_queue_space();
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devc.disable_pcap_loopback();
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devc.enable_pcap_non_secure_mode();
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// load pcap
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//devc.wait_for_dma_transfer();
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}
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@ -1,8 +1,9 @@
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use core::fmt;
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use libregister::*;
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mod regs;
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use crate::println;
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pub struct DevC {
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regs: &'static mut regs::RegisterBlock,
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}
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@ -14,16 +15,117 @@ impl DevC {
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}
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}
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pub fn enable(&mut self) {
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pub fn enable_and_select_pcap(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_mode(true)
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.pcap_pr(true)
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.pcap_pr(true)
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})
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}
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pub fn disable(&mut self) {
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pub fn enable_and_select_icap(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_mode(false)
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w.pcap_mode(true)
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.pcap_pr(false)
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})
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}
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pub fn clear_interrupts(&mut self) {
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self.regs.int_sts.modify(|_, w| {
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w.pps_gts_usr_b_int(true)
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.pps_fst_cfg_b_int(true)
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.pps_gpwrdwn_b_int(true)
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.pps_gts_cfg_b_int(true)
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.pps_cfg_reset_b_int(true)
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.ixr_axi_wto(true)
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.ixr_axi_werr(true)
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.ixr_axi_rto(true)
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.ixr_axi_rerr(true)
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.ixr_rx_fifo_ov(true)
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.ixr_wr_fifo_lvl(true)
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.ixr_rd_fifo_lvl(true)
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.ixr_dma_cmd_err(true)
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.ixr_dma_q_ov(true)
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.ixr_dma_done(true)
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.ixr_d_p_done(true)
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.ixr_p2d_len_err(true)
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.ixr_pcfg_hmac_err(true)
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.ixr_pcfg_seu_err(true)
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.ixr_pcfg_por_b(true)
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.ixr_pcfg_cfg_rst(true)
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.ixr_pcfg_done(true)
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.ixr_pcfg_init_pe(true)
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.ixr_pcfg_init_ne(true)
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})
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}
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pub fn initialize_pl(&mut self) {
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self.regs.mctrl.modify(|_, w| {
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w.pcfg_por_b(true)
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.pcfg_por_b(false)
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});
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self.wait_for_status_pcfg_init_to_be(false);
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self.regs.mctrl.modify(|_, w| {
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w.pcfg_por_b(true)
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});
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self.regs.int_sts.modify(|_,w| {
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w.ixr_pcfg_done(true)
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});
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}
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pub fn wait_for_pl_to_be_ready(&self) {
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self.wait_for_status_pcfg_init_to_be(true)
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}
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pub fn wait_for_command_queue_space(&self){
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self.wait_for_status_dma_cmd_q_f_to_be(false);
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}
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pub fn disable_pcap_loopback(&mut self) {
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self.regs.mctrl.modify(|_,w| {
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w.pcap_lpbk(false)
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});
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}
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pub fn enable_pcap_secure_mode(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_rate_en(true)
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});
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}
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pub fn enable_pcap_non_secure_mode(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_rate_en(false)
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});
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}
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pub fn wait_for_dma_transfer(&self) {
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self.wait_for_int_sts_ixr_dma_done_to_be(true);
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}
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fn wait_for_status_pcfg_init_to_be(&self, value: bool) {
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loop {
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let status = self.regs.status.read();
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println!("expected value: {}, actual pcfg_init: {}",value, status.pcfg_init());
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if value == status.pcfg_init() {
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return
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}
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}
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}
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fn wait_for_status_dma_cmd_q_f_to_be(&self, value: bool) {
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loop {
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let status = self.regs.status.read();
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if value == status.pcfg_init() {
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return
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}
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}
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}
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fn wait_for_int_sts_ixr_dma_done_to_be(&self, value: bool) {
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loop {
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let int_sts = self.regs.int_sts.read();
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if value == int_sts.ixr_dma_done() {
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return
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}
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}
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}
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}
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@ -101,7 +101,7 @@ register_bit!(int_sts, ixr_pcfg_hmac_err, 6);
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register_bit!(int_sts, ixr_pcfg_seu_err, 5);
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register_bit!(int_sts, ixr_pcfg_por_b, 4);
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register_bit!(int_sts, ixr_pcfg_cfg_rst, 3);
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register_bit!(int_sts, ixr_pcfg_done, 2);
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register_bit!(int_sts, ixr_pcfg_done, 2); // seems to be PCFG_DONE_INT on pg 218 in TRM
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register_bit!(int_sts, ixr_pcfg_init_pe, 1);
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register_bit!(int_sts, ixr_pcfg_init_ne, 0);
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@ -1 +1,16 @@
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use core::fmt;
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use libregister::*;
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mod regs;
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pub struct DmaC {
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regs: &'static mut regs::RegisterBlock,
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}
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impl DmaC {
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pub fn new() -> Self {
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DmaC {
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regs: regs::RegisterBlock::dmac0_ns(),
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}
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}
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}
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@ -4,6 +4,7 @@ pub mod slcr;
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pub mod clocks;
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pub mod uart;
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pub mod devc;
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pub mod dmac;
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pub mod stdio;
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pub mod eth;
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pub mod axi_hp;
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