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3e02980c20
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4e1f46b3e2
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@ -183,14 +183,6 @@ impl DdrRam {
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/// Reset DDR controller
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fn reset_ddrc(&mut self) {
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#[cfg(feature = "target_zc706")]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000777);
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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@ -217,11 +209,9 @@ impl DdrRam {
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0x0010_0000 as *mut _
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}
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/// actually there's 1 MB more but starting at 0x0000_0000
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/// overlaps with OCM.
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pub fn size(&self) -> usize {
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#[cfg(feature = "target_zc706")]
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let megabytes = 1022;
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let megabytes = 511;
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#[cfg(feature = "target_cora_z7_10")]
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let megabytes = 511;
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@ -123,7 +123,7 @@ impl L1Table {
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bufferable: true,
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});
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/* (DDR cacheable) */
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for ddr in 1..=0x3ff {
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for ddr in 1..=0x1ff {
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self.direct_mapped_section(ddr, L1Section {
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global: true,
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shareable: true,
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@ -135,6 +135,19 @@ impl L1Table {
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bufferable: false,
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});
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}
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/* (unassigned/reserved). */
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for undef in 0x1ff..=0x3ff {
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self.direct_mapped_section(undef, L1Section {
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global: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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tex: 0,
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domain: 0,
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exec: false,
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cacheable: false,
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bufferable: false,
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});
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}
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/* 0x40000000 - 0x7fffffff (FPGA slave0) */
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for fpga_slave in 0x400..=0x7ff {
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self.direct_mapped_section(fpga_slave, L1Section {
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