Compare commits
No commits in common. "3180f1c3f766d8113763ba3223e2cddaf71b219e" and "6ffcf7d4a4a8bfb549517aa68e9609b03eabcfaf" have entirely different histories.
3180f1c3f7
...
6ffcf7d4a4
|
@ -1,67 +0,0 @@
|
||||||
//! Quad-SPI Flash Controller
|
|
||||||
|
|
||||||
use crate::regs::{RegisterW, RegisterRW};
|
|
||||||
use super::slcr;
|
|
||||||
use super::clocks::CpuClocks;
|
|
||||||
|
|
||||||
pub mod regs;
|
|
||||||
|
|
||||||
/// Flash Interface Driver
|
|
||||||
pub struct Flash {
|
|
||||||
regs: &'static mut regs::RegisterBlock,
|
|
||||||
}
|
|
||||||
|
|
||||||
impl Flash {
|
|
||||||
pub fn new(clock: u32) -> Self {
|
|
||||||
Self::enable_clocks(clock);
|
|
||||||
Self::setup_signals();
|
|
||||||
Self::reset();
|
|
||||||
|
|
||||||
let regs = regs::RegisterBlock::qspi();
|
|
||||||
let mut flash = Flash { regs };
|
|
||||||
flash.configure();
|
|
||||||
flash
|
|
||||||
}
|
|
||||||
|
|
||||||
fn enable_clocks(clock: u32) {
|
|
||||||
let io_pll = CpuClocks::get().io;
|
|
||||||
let divisor = ((clock - 1 + io_pll) / clock)
|
|
||||||
.max(1).min(63) as u8;
|
|
||||||
|
|
||||||
slcr::RegisterBlock::unlocked(|slcr| {
|
|
||||||
slcr.lqspi_clk_ctrl.write(
|
|
||||||
slcr::LqspiClkCtrl::zeroed()
|
|
||||||
.src_sel(slcr::PllSource::IoPll)
|
|
||||||
.divisor(divisor)
|
|
||||||
.clkact(true)
|
|
||||||
);
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
fn setup_signals() {
|
|
||||||
// TODO
|
|
||||||
}
|
|
||||||
|
|
||||||
fn reset() {
|
|
||||||
slcr::RegisterBlock::unlocked(|slcr| {
|
|
||||||
slcr.lqspi_rst_ctrl.write(
|
|
||||||
slcr::LqspiRstCtrl::zeroed()
|
|
||||||
.ref_rst(true)
|
|
||||||
.cpu1x_rst(true)
|
|
||||||
);
|
|
||||||
slcr.lqspi_rst_ctrl.write(
|
|
||||||
slcr::LqspiRstCtrl::zeroed()
|
|
||||||
);
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
fn configure(&mut self) {
|
|
||||||
self.regs.config.modify(|_, w| w
|
|
||||||
.baud_rate_div(4 /* TODO */)
|
|
||||||
.mode_sel(true)
|
|
||||||
.leg_flsh(true)
|
|
||||||
.endian(false)
|
|
||||||
.fifo_width(0b11)
|
|
||||||
);
|
|
||||||
}
|
|
||||||
}
|
|
|
@ -1,78 +0,0 @@
|
||||||
use volatile_register::{RO, WO, RW};
|
|
||||||
|
|
||||||
use crate::{register, register_bit, register_bits, register_bits_typed};
|
|
||||||
|
|
||||||
#[repr(C)]
|
|
||||||
pub struct RegisterBlock {
|
|
||||||
pub config: Config,
|
|
||||||
pub intr_status: RW<u32>,
|
|
||||||
pub intr_en: RW<u32>,
|
|
||||||
pub intr_dis: RW<u32>,
|
|
||||||
pub intr_mask: RO<u32>,
|
|
||||||
pub enable: RW<u32>,
|
|
||||||
pub delay: RW<u32>,
|
|
||||||
pub txd0: WO<u32>,
|
|
||||||
pub rx_data: RO<u32>,
|
|
||||||
pub slave_idle_count: RW<u32>,
|
|
||||||
pub tx_thres: RW<u32>,
|
|
||||||
pub rx_thes: RW<u32>,
|
|
||||||
pub gpio: RW<u32>,
|
|
||||||
pub _unused1: RO<u32>,
|
|
||||||
pub lpbk_dly_adj: RW<u32>,
|
|
||||||
pub _unused2: [RO<u32>; 17],
|
|
||||||
pub txd1: WO<u32>,
|
|
||||||
pub txd2: WO<u32>,
|
|
||||||
pub txd3: WO<u32>,
|
|
||||||
pub _unused3: [RO<u32>; 5],
|
|
||||||
pub lqspi_cfg: RW<u32>,
|
|
||||||
pub lqspi_sts: RW<u32>,
|
|
||||||
pub _unused4: [RO<u32>; 21],
|
|
||||||
pub mod_id: RW<u32>,
|
|
||||||
}
|
|
||||||
|
|
||||||
impl RegisterBlock {
|
|
||||||
const BASE_ADDRESS: *mut Self = 0xE000D000 as *mut _;
|
|
||||||
|
|
||||||
pub fn qspi() -> &'static mut Self {
|
|
||||||
unsafe { &mut *Self::BASE_ADDRESS }
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
register!(config, Config, RW, u32);
|
|
||||||
register_bit!(config,
|
|
||||||
/// Enables master mode
|
|
||||||
mode_sel, 0);
|
|
||||||
register_bit!(config,
|
|
||||||
/// Clock polarity low/high
|
|
||||||
clk_pol, 1);
|
|
||||||
register_bit!(config,
|
|
||||||
/// Clock phase
|
|
||||||
clk_ph, 2);
|
|
||||||
register_bits!(config,
|
|
||||||
/// divisor = 2 ** (1 + baud_rate_div)
|
|
||||||
baud_rate_div, u8, 3, 5);
|
|
||||||
register_bits!(config,
|
|
||||||
/// Must be set to 0b11
|
|
||||||
fifo_width, u8, 6, 7);
|
|
||||||
register_bit!(config,
|
|
||||||
/// Must be 0
|
|
||||||
ref_clk, 8);
|
|
||||||
register_bit!(config,
|
|
||||||
/// Peripheral Chip Select Line
|
|
||||||
pcs, 10);
|
|
||||||
register_bit!(config,
|
|
||||||
/// false: auto mode, true: manual CS mode
|
|
||||||
manual_cs, 14);
|
|
||||||
register_bit!(config,
|
|
||||||
/// false: auto mode, true: enables manual start enable
|
|
||||||
man_start_en, 15);
|
|
||||||
register_bit!(config,
|
|
||||||
/// false: auto mode, true: enables manual start command
|
|
||||||
man_start_com, 16);
|
|
||||||
register_bit!(config, holdb_dr, 19);
|
|
||||||
register_bit!(config,
|
|
||||||
/// false: little, true: endian
|
|
||||||
endian, 26);
|
|
||||||
register_bit!(config,
|
|
||||||
/// false: legacy SPI mode, true: Flash memory interface mode
|
|
||||||
leg_flsh, 31);
|
|
|
@ -6,4 +6,3 @@ pub mod axi_hp;
|
||||||
pub mod axi_gp;
|
pub mod axi_gp;
|
||||||
pub mod ddr;
|
pub mod ddr;
|
||||||
pub mod mpcore;
|
pub mod mpcore;
|
||||||
pub mod flash;
|
|
||||||
|
|
|
@ -84,7 +84,7 @@ pub struct RegisterBlock {
|
||||||
pub gem0_clk_ctrl: GemClkCtrl,
|
pub gem0_clk_ctrl: GemClkCtrl,
|
||||||
pub gem1_clk_ctrl: GemClkCtrl,
|
pub gem1_clk_ctrl: GemClkCtrl,
|
||||||
pub smc_clk_ctrl: RW<u32>,
|
pub smc_clk_ctrl: RW<u32>,
|
||||||
pub lqspi_clk_ctrl: LqspiClkCtrl,
|
pub lqspi_clk_ctrl: RW<u32>,
|
||||||
pub sdio_clk_ctrl: RW<u32>,
|
pub sdio_clk_ctrl: RW<u32>,
|
||||||
pub uart_clk_ctrl: UartClkCtrl,
|
pub uart_clk_ctrl: UartClkCtrl,
|
||||||
pub spi_clk_ctrl: RW<u32>,
|
pub spi_clk_ctrl: RW<u32>,
|
||||||
|
@ -124,7 +124,7 @@ pub struct RegisterBlock {
|
||||||
pub i2c_rst_ctrl: RW<u32>,
|
pub i2c_rst_ctrl: RW<u32>,
|
||||||
pub uart_rst_ctrl: UartRstCtrl,
|
pub uart_rst_ctrl: UartRstCtrl,
|
||||||
pub gpio_rst_ctrl: RW<u32>,
|
pub gpio_rst_ctrl: RW<u32>,
|
||||||
pub lqspi_rst_ctrl: LqspiRstCtrl,
|
pub lqspi_rst_ctrl: RW<u32>,
|
||||||
pub smc_rst_ctrl: RW<u32>,
|
pub smc_rst_ctrl: RW<u32>,
|
||||||
pub ocm_rst_ctrl: RW<u32>,
|
pub ocm_rst_ctrl: RW<u32>,
|
||||||
reserved4: [u32; 1],
|
reserved4: [u32; 1],
|
||||||
|
@ -134,7 +134,7 @@ pub struct RegisterBlock {
|
||||||
pub rs_awdt_ctrl: RW<u32>,
|
pub rs_awdt_ctrl: RW<u32>,
|
||||||
reserved6: [u32; 2],
|
reserved6: [u32; 2],
|
||||||
pub reboot_status: RW<u32>,
|
pub reboot_status: RW<u32>,
|
||||||
pub boot_mode: BootMode,
|
pub boot_mode: RW<u32>,
|
||||||
reserved7: [u32; 40],
|
reserved7: [u32; 40],
|
||||||
pub apu_ctrl: RW<u32>,
|
pub apu_ctrl: RW<u32>,
|
||||||
pub wdt_clk_sel: RW<u32>,
|
pub wdt_clk_sel: RW<u32>,
|
||||||
|
@ -440,15 +440,6 @@ impl UartRstCtrl {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
register!(lqspi_clk_ctrl, LqspiClkCtrl, RW, u32);
|
|
||||||
register_bit!(lqspi_clk_ctrl, clkact, 0);
|
|
||||||
register_bits_typed!(lqspi_clk_ctrl, src_sel, u8, PllSource, 4, 5);
|
|
||||||
register_bits!(lqspi_clk_ctrl, divisor, u8, 8, 13);
|
|
||||||
|
|
||||||
register!(lqspi_rst_ctrl, LqspiRstCtrl, RW, u32);
|
|
||||||
register_bit!(lqspi_rst_ctrl, ref_rst, 1);
|
|
||||||
register_bit!(lqspi_rst_ctrl, cpu1x_rst, 0);
|
|
||||||
|
|
||||||
register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32);
|
register!(a9_cpu_rst_ctrl, A9CpuRstCtrl, RW, u32);
|
||||||
register_bit!(a9_cpu_rst_ctrl, peri_rst, 8);
|
register_bit!(a9_cpu_rst_ctrl, peri_rst, 8);
|
||||||
register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5);
|
register_bit!(a9_cpu_rst_ctrl, a9_clkstop1, 5);
|
||||||
|
@ -456,20 +447,6 @@ register_bit!(a9_cpu_rst_ctrl, a9_clkstop0, 4);
|
||||||
register_bit!(a9_cpu_rst_ctrl, a9_rst1, 1);
|
register_bit!(a9_cpu_rst_ctrl, a9_rst1, 1);
|
||||||
register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
|
register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
|
||||||
|
|
||||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
||||||
#[repr(u8)]
|
|
||||||
pub enum BootModePins {
|
|
||||||
Jtag = 0b000,
|
|
||||||
Nor = 0b001,
|
|
||||||
Nand = 0b010,
|
|
||||||
QuadSpi = 0b100,
|
|
||||||
SdCard = 0b110,
|
|
||||||
}
|
|
||||||
|
|
||||||
register!(boot_mode, BootMode, RO, u32);
|
|
||||||
register_bit!(boot_mode, pll_bypass, 4);
|
|
||||||
register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 3);
|
|
||||||
|
|
||||||
register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
|
register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
|
||||||
register_bit!(pss_rst_ctrl, soft_rst, 1);
|
register_bit!(pss_rst_ctrl, soft_rst, 1);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue