68 lines
1.6 KiB
Rust
68 lines
1.6 KiB
Rust
//! Quad-SPI Flash Controller
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use crate::regs::{RegisterW, RegisterRW};
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use super::slcr;
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use super::clocks::CpuClocks;
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pub mod regs;
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/// Flash Interface Driver
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pub struct Flash {
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regs: &'static mut regs::RegisterBlock,
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}
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impl Flash {
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pub fn new(clock: u32) -> Self {
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Self::enable_clocks(clock);
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Self::setup_signals();
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Self::reset();
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let regs = regs::RegisterBlock::qspi();
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let mut flash = Flash { regs };
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flash.configure();
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flash
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}
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fn enable_clocks(clock: u32) {
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let io_pll = CpuClocks::get().io;
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let divisor = ((clock - 1 + io_pll) / clock)
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.max(1).min(63) as u8;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_clk_ctrl.write(
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slcr::LqspiClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor(divisor)
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.clkact(true)
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);
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});
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}
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fn setup_signals() {
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// TODO
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}
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fn reset() {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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.ref_rst(true)
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.cpu1x_rst(true)
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);
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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);
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});
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}
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fn configure(&mut self) {
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self.regs.config.modify(|_, w| w
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.baud_rate_div(4 /* TODO */)
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.mode_sel(true)
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.leg_flsh(true)
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.endian(false)
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.fifo_width(0b11)
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);
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}
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}
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