 Astro
|
3279aab961
|
main: refactor into abort, panic, ram
|
2019-11-11 02:46:18 +01:00 |
|
Astro
|
3eb7fce572
|
delint
|
2019-11-11 01:42:38 +01:00 |
|
Astro
|
4d3b2ac7e5
|
zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
|
2019-11-11 00:06:35 +01:00 |
|
Astro
|
261455877d
|
zynq::ddr: fix DDR 3x/2x setup, print clocks
|
2019-11-07 00:13:50 +01:00 |
|
Astro
|
ff96bf903b
|
zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
|
2019-11-07 00:13:50 +01:00 |
|
Astro
|
d2df5652d0
|
Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4.
|
2019-11-07 00:13:50 +01:00 |
|
Astro
|
961e2e1dd0
|
zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
|
2019-11-03 02:23:16 +01:00 |
|
Astro
|
6bee1f44f4
|
zynq: replace unnecessary slcr::unlocked with new
|
2019-10-31 20:48:07 +01:00 |
|
Astro
|
e248d3d3b1
|
zynq::ddr: optimize memtest
|
2019-10-31 01:32:45 +01:00 |
|
Astro
|
91bab76ab6
|
zynq::ddr: fix usable ram size
|
2019-10-31 01:27:49 +01:00 |
|
Astro
|
ceeaa6427e
|
zynq::ddr: fix typo
|
2019-10-28 23:58:25 +01:00 |
|
Astro
|
fc39885d3b
|
zynq::ddr: fix clock setup
|
2019-10-28 00:43:09 +01:00 |
|
Astro
|
f199ac68b4
|
zynq::ddr: don't overwrite slcr.ddr_pll_ctrl
|
2019-10-27 22:54:34 +01:00 |
|
Astro
|
637bb35f43
|
zynq::ddr: fix memtest progress calculation
|
2019-10-27 20:38:35 +01:00 |
|
Astro
|
85bd506132
|
zynq::ddr: parameters
|
2019-10-27 20:38:06 +01:00 |
|
Astro
|
9b4f07f37c
|
zynq::ddr, main: parameters, memtest
|
2019-10-25 23:19:34 +02:00 |
|
Astro
|
a4d3360a70
|
zynq::slcr: implement Display for PllStatus
|
2019-10-25 20:38:10 +02:00 |
|
Astro
|
838434cdec
|
zynq::ddr: wait for init
|
2019-10-25 19:15:22 +02:00 |
|
Astro
|
4cf5283ba8
|
zynq::ddr: implement reset_ddrc(), add to main
|
2019-10-24 01:39:14 +02:00 |
|
Astro
|
a8886de067
|
zynq::ddr: implement configure_iob()
|
2019-10-24 01:24:12 +02:00 |
|
Astro
|
afda48e3fe
|
zynq::ddr: add clock_setup(), calibrate_iob_impedance()
|
2019-10-22 01:25:35 +02:00 |
|
Astro
|
c046bbf8a2
|
move slcr, clocks, uart, eth into src/zynq/
|
2019-10-21 22:19:03 +02:00 |
|
Astro
|
9d725bcf0f
|
zynq::ddr: init with clock setup
|
2019-10-21 22:12:10 +02:00 |