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zynq-rs
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Update EMIO to Emio

This commit is contained in:
newell 2024-09-27 18:55:32 -07:00
parent 8f2dc94cf8
commit db22dafe28
2 changed files with 3 additions and 3 deletions
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4
libboard_zynq/src/clocks/mod.rs
View File

@ -103,7 +103,7 @@ impl Clocks {
self.ddr, self.ddr,
slcr::PllSource::IoPll => slcr::PllSource::IoPll =>
self.io, self.io,
slcr::PllSource::EMIO => slcr::PllSource::Emio =>
unimplemented!(), unimplemented!(),
}; };
pll / u32::from(uart_clk_ctrl.divisor()) pll / u32::from(uart_clk_ctrl.divisor())
@ -119,7 +119,7 @@ impl Clocks {
self.ddr, self.ddr,
slcr::PllSource::IoPll => slcr::PllSource::IoPll =>
self.io, self.io,
slcr::PllSource::EMIO => slcr::PllSource::Emio =>
unimplemented!(), unimplemented!(),
}; };
pll / u32::from(sdio_clk_ctrl.divisor()) pll / u32::from(sdio_clk_ctrl.divisor())

2
libboard_zynq/src/eth/mod.rs
View File

@ -75,7 +75,7 @@ impl Gem for Gem0 {
#[cfg(feature = "target_ebaz4205")] #[cfg(feature = "target_ebaz4205")]
slcr::GemClkCtrl::zeroed() slcr::GemClkCtrl::zeroed()
.clkact(true) .clkact(true)
.srcsel(slcr::PllSource::EMIO) .srcsel(slcr::PllSource::Emio)
.divisor(divisor0 as u8) .divisor(divisor0 as u8)
.divisor1(divisor1 as u8) .divisor1(divisor1 as u8)
); );