From db22dafe28ada15a4147d11a44ec6504d02ed4b3 Mon Sep 17 00:00:00 2001
From: newell <newell.jensen@gmail.com>
Date: Fri, 27 Sep 2024 18:55:32 -0700
Subject: [PATCH] Update EMIO to Emio

---
 libboard_zynq/src/clocks/mod.rs | 4 ++--
 libboard_zynq/src/eth/mod.rs    | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/libboard_zynq/src/clocks/mod.rs b/libboard_zynq/src/clocks/mod.rs
index 24b9a56..bc507c4 100644
--- a/libboard_zynq/src/clocks/mod.rs
+++ b/libboard_zynq/src/clocks/mod.rs
@@ -103,7 +103,7 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
-            slcr::PllSource::EMIO =>
+            slcr::PllSource::Emio =>
                 unimplemented!(),
         };
         pll / u32::from(uart_clk_ctrl.divisor())
@@ -119,7 +119,7 @@ impl Clocks {
                 self.ddr,
             slcr::PllSource::IoPll =>
                 self.io,
-            slcr::PllSource::EMIO =>
+            slcr::PllSource::Emio =>
                 unimplemented!(),
         };
         pll / u32::from(sdio_clk_ctrl.divisor())
diff --git a/libboard_zynq/src/eth/mod.rs b/libboard_zynq/src/eth/mod.rs
index 0f6fa45..8dc0f62 100644
--- a/libboard_zynq/src/eth/mod.rs
+++ b/libboard_zynq/src/eth/mod.rs
@@ -75,7 +75,7 @@ impl Gem for Gem0 {
                 #[cfg(feature = "target_ebaz4205")]
                 slcr::GemClkCtrl::zeroed()
                     .clkact(true)
-                    .srcsel(slcr::PllSource::EMIO)
+                    .srcsel(slcr::PllSource::Emio)
                     .divisor(divisor0 as u8)
                     .divisor1(divisor1 as u8)
             );