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zynq-rs
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libboard_zynq: fix ddr memtest range

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Astro 2020-05-09 02:53:58 +02:00
parent 3e02980c20
commit 3841accd9c
1 changed files with 3 additions and 3 deletions
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6
libboard_zynq/src/ddr/mod.rs
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@ -221,7 +221,7 @@ impl DdrRam {
/// overlaps with OCM. /// overlaps with OCM.
pub fn size(&self) -> usize { pub fn size(&self) -> usize {
#[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
let megabytes = 1022; let megabytes = 1023;
#[cfg(feature = "target_cora_z7_10")] #[cfg(feature = "target_cora_z7_10")]
let megabytes = 511; let megabytes = 511;
@ -237,9 +237,9 @@ impl DdrRam {
for (i, pattern) in patterns.iter().enumerate() { for (i, pattern) in patterns.iter().enumerate() {
info!("memtest phase {} (status: {:?})", i, self.status()); info!("memtest phase {} (status: {:?})", i, self.status());
for megabyte in 0..=(slice.len() / (1024 * 1024)) { for megabyte in 0..slice.len() / (1024 * 1024) {
let start = megabyte * 1024 * 1024 / 4; let start = megabyte * 1024 * 1024 / 4;
let end = ((megabyte + 1) * 1024 * 1024 / 4).min(slice.len()); let end = ((megabyte + 1) * 1024 * 1024 / 4);
for b in slice[start..end].iter_mut() { for b in slice[start..end].iter_mut() {
expected.map(|expected| { expected.map(|expected| {
let read: u32 = *b; let read: u32 = *b;