M-Labs/zynq-rs
11
0
Fork 15
Code Issues 6 Pull Requests Releases Wiki Activity

zynq::ddr: fix DDR 3x/2x setup, print clocks

Browse Source
This commit is contained in:
Astro 2019-11-06 23:05:29 +01:00
parent ff96bf903b
commit 261455877d
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/zynq/ddr/mod.rs
View File

@ -42,8 +42,9 @@ impl DdrRam {
let clocks = CpuClocks::get(); let clocks = CpuClocks::get();
println!("Clocks: {:?}", clocks); println!("Clocks: {:?}", clocks);
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8; let ddr3x_clk_divisor = ((DDR_FREQ - 1 + clocks.ddr) / DDR_FREQ).min(255) as u8;
let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2; let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
slcr.ddr_clk_ctrl.write( slcr.ddr_clk_ctrl.write(
@ -64,6 +65,7 @@ impl DdrRam {
.max(1).min(63) as u8; .max(1).min(63) as u8;
let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0)) let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
.max(1).min(63) as u8; .max(1).min(63) as u8;
println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// Step 1. // Step 1.