f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs
2019-06-26 00:51:37 +03:00
298a8b6f6e
Provide write() for mepc
2019-06-25 23:48:47 +03:00
7a8d3d1f6c
Implement mscratch and mtval registers
2019-06-25 23:48:27 +03:00
00367d4fd2
Add sections to the registers module
2019-06-25 23:34:47 +03:00
370a654d2c
Regenerate binaries
2019-06-25 23:34:20 +03:00
a659a0cc39
Declare all the CSR registers in asm.S
2019-06-25 23:33:40 +03:00
ac2ac6756b
Derive useful traits for enums
2019-06-25 23:32:51 +03:00
5a1ab837b4
Merge #28
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28: Add marchid, mhartid and mimpid registers r=laanwj a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-06-25 19:40:12 +00:00
2965734b7b
Bump version (0.5.3)
2019-04-29 10:45:19 +02:00
2ef11206bd
Regenerate binaries
2019-04-29 10:44:45 +02:00
cf9008492a
Add marchid, mhartid and mimpid registers
2019-04-29 10:43:51 +02:00
1e514648fd
Merge #26
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26: Fix Misa::has_extension() r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-04-01 19:06:47 +00:00
c3ff23989e
Bump version (0.5.2)
2019-04-01 19:59:10 +03:00
ca797a35d8
Fix Misa::has_extension()
2019-04-01 19:58:40 +03:00
33070435a0
Merge #25
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25: Rename RISCV to RISC-V in documentation r=Disasm a=medusacle
More common name for the CPU architecture 😄 Also update the copyright year.
Probably, if this is merged, you'd want to update the project description as well.
Co-authored-by: mara <vmedea@protonmail.com>
2019-03-28 21:20:43 +00:00
6425cab701
Merge #24
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24: Add FS and XS fields, fix incorrect field setting, bump version r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-28 20:47:36 +00:00
c1a3fe2dd9
Rename RISCV to RISC-V
2019-03-28 18:31:57 +01:00
6bfccad567
Bump version (0.5.1)
2019-03-28 19:06:40 +03:00
7112ef8af2
Regenerate blobs
2019-03-28 18:57:28 +03:00
5baba0cb32
Add write function for sstatus register
2019-03-28 18:56:49 +03:00
9bb3b5803c
Refactoring: use set_bits() in set_fs function
2019-03-28 17:59:07 +03:00
5ef90e3189
Fix set_spp and set_mpp functions
2019-03-28 17:57:40 +03:00
6a2bdbf38d
Refactoring
2019-03-18 18:25:16 +03:00
4fb81f4860
Add FS and XS fields of mstatus
2019-03-18 18:14:00 +03:00
32eba6c1ea
Merge #23
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23: Add fcsr register r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-17 18:47:24 +00:00
8222812d8d
Regenerate blobs
2019-03-17 19:06:48 +03:00
4ad2150a24
Add fcsr register
2019-03-17 19:06:29 +03:00
037e8bdcf4
Merge #22
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22: Update CI, add MSRV policy r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-17 14:47:55 +00:00
7d4919a67c
Add MSRV policy
2019-03-17 17:29:48 +03:00
799cdaf6d2
Fix docs
2019-03-17 17:28:05 +03:00
698cb306ea
Enable gcc caching
2019-03-17 17:24:07 +03:00
87453e6b0a
Change PATH in CI script
2019-03-17 16:52:15 +03:00
a8040bd24b
Check blobs in separate target
2019-03-17 16:45:28 +03:00
9352831150
Simplify CI scripts
2019-03-17 16:30:23 +03:00
41b4c1c1e6
Remove useless 'set' commands
2019-03-17 16:28:53 +03:00
662dcb67d2
Update Travis build matrix
2019-03-17 16:27:41 +03:00
2450868523
Merge #21
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21: Add 64-bit targets, reads for composite CSRs, bump version r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-01 15:40:36 +00:00
a091d236dd
Bump version
2019-03-01 17:48:59 +03:00
925c496949
Read composite CSRs as one 64-bit value
2019-03-01 17:46:35 +03:00
b665adeb95
Refactoring: use get_bit() instead of shifts
2019-03-01 17:10:45 +03:00
ab15a6a8c7
CI: check new targets
2019-03-01 17:02:13 +03:00
427c3b9035
Generate binaries for 64-bit targets
2019-03-01 17:00:36 +03:00
70bdf2f2f7
Merge #20
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20: move doc comments inside macro invocations r=Disasm a=euclio
[rust-lang/rust#57882 ](https://github.com/rust-lang/rust/pull/57882 ) is modifying the `unused_doc_comments` lint to fire on mistakenly documented macro expansions. Note that these doc comments are not currently used, since they are eliminated when the macro is expanded. A crater run detected that this crate will break due to this change, likely because of the use of `deny(unused_doc_comments)` or `deny(warnings)`.
While this kind of breakage is allowed under Rust's stability guarantees, I am opening PRs to affected crates to reduce the impact.
This PR protects your crate from future breakage by moving the offending doc comments inside the macro invocations.
Co-authored-by: Andy Russell <arussell123@gmail.com>
2019-02-19 20:31:01 +00:00
8cbb3878e5
move doc comments inside macro invocations
2019-02-19 15:19:02 -05:00
c99d70bf02
Merge #19
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19: Add team e-mail to authors r=dvc94ch a=Disasm
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-02-07 16:55:23 +00:00
e2ed39decd
Leave just team e-mail in authors
2019-02-07 19:53:22 +03:00
8d6b2fe111
Add team e-mail to authors
2019-02-06 22:20:15 +03:00
1ee535e94f
Merge #18
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18: remove the unused 'const-fn' feature r=Disasm a=japaric
note that is technically a breaking change
Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2019-02-06 16:03:42 +00:00
01cfa71fd0
remove the unused 'const-fn' feature
2019-02-06 16:48:23 +01:00
4e3517aaec
Merge #17
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17: Update docs and bump version r=dvc94ch a=Disasm
cc @rust-embedded/riscv
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-01-24 14:37:18 +00:00
Vadim Kaushan
bors[bot]
bors[bot]
mara
Andy Russell
Jorge Aparicio