5 Commits

Author	SHA1	Message	Date
Vadim Kaushan	ac1cba597a	Fix RISC-V name ... https://riscv.org/risc-v-trademark-usage/	2019-01-24 17:19:32 +03:00
Vadim Kaushan	41378757c0	Do not require const-fn and asm features	2019-01-23 01:29:54 +03:00
WangRunji	8776d30d3b	add S-Mode registers ... - use macros to simplify CSR ops - use crate 'bit_field' to make bits operation clear	2018-11-09 22:42:46 +08:00
David Craven	7db0e71060	New api.	2018-03-27 20:17:44 +02:00
David Craven	e864581828	Initial commit.	2017-09-19 16:23:35 +02:00