Initial commit.
This commit is contained in:
David Craven
commit
e864581828
2
.gitignore
vendored
Normal file
2
.gitignore
vendored
Normal file
@ -0,0 +1,2 @@
|
||||
Cargo.lock
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||||
target/
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13
Cargo.toml
Normal file
13
Cargo.toml
Normal file
@ -0,0 +1,13 @@
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[package]
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name = "riscv"
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version = "0.1.0"
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repository = "https://github.com/dvc94ch/riscv"
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authors = ["David Craven <david@craven.ch>"]
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categories = ["embedded", "hardware-support", "no-std"]
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description = "Low level access to RISCV processors"
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keywords = ["riscv", "register", "peripheral"]
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license = "ISC"
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[dependencies]
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bare-metal = "0.1.0"
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volatile-register = "0.2.0"
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18
README.md
Normal file
18
README.md
Normal file
@ -0,0 +1,18 @@
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# `riscv`
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> Low level access to RISCV processors
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# License
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Copyright 2017 David Craven
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Permission to use, copy, modify, and/or distribute this software for any purpose
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with or without fee is hereby granted, provided that the above copyright notice
|
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and this permission notice appear in all copies.
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||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
|
||||
REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
||||
FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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||||
INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
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||||
OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
|
||||
THIS SOFTWARE.
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32
src/asm.rs
Normal file
32
src/asm.rs
Normal file
@ -0,0 +1,32 @@
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//! Assembly instructions
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macro_rules! instruction {
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($fnname:ident, $asm:expr) => (
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#[inline(always)]
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pub fn $fnname() {
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match () {
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#[cfg(target_arch = "riscv")]
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() => unsafe {
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asm!($asm :::: "volatile");
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},
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#[cfg(not(target_arch = "riscv"))]
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() => {}
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}
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}
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)
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}
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/// User Level ISA instructions
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instruction!(nop, "addi zero, zero, 0");
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instruction!(ecall, "ecall");
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instruction!(ebreak, "ebreak");
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instruction!(fence, "fence iorw, iorw");
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instruction!(fencei, "fence.i");
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/// Priviledged ISA Instructions
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instruction!(wfi, "wfi");
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instruction!(uret, "uret");
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instruction!(sret, "sret");
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instruction!(mret, "mret");
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instruction!(sfencevma, "sfence.vma");
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596
src/csr.rs
Normal file
596
src/csr.rs
Normal file
@ -0,0 +1,596 @@
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//! Functions for accessing Control and Status Registers
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macro_rules! csr_asm {
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($op:ident, $csr:expr, $value:expr) => (
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{
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let res: usize;
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unsafe {
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asm!(concat!(stringify!($op), " $0, ", stringify!($csr), ", $1")
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: "=r"(res)
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: "r"($value)
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:
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: "volatile");
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}
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res
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}
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)
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}
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macro_rules! r {
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($MOD:ident, $TYPE:ident, $CSR:expr) => (
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pub struct R {
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bits: u32,
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}
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impl super::$TYPE {
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#[inline(always)]
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pub fn read(&self) -> R {
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R { bits: csr_asm!(csrrs, $CSR, 0) as u32 }
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}
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}
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impl R {
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#[inline(always)]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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}
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)
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}
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macro_rules! w {
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($MOD:ident, $TYPE:ident, $CSR:expr) => (
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macro_rules! func {
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($fnname:ident, $csrop:ident) => (
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#[inline(always)]
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pub fn $fnname<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W { bits: 0 };
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f(&mut w);
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csr_asm!($csrop, $CSR, w.bits as usize);
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}
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)
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}
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pub struct W {
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||||
bits: u32,
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}
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impl super::$TYPE {
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func!(write, csrrw);
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func!(set, csrrs);
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func!(clear, csrrc);
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}
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impl W {
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||||
#[inline(always)]
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pub fn bits(&mut self, value: u32) -> &mut W {
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self.bits = value;
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self
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||||
}
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#[inline(always)]
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||||
pub fn set_bits(&mut self, value: u32) -> &mut W {
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self.bits |= value;
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self
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||||
}
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#[inline(always)]
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||||
pub fn clear_bits(&mut self, value: u32) -> &mut W {
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||||
self.bits &= !value;
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self
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||||
}
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||||
}
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||||
)
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}
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macro_rules! rw {
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($MOD:ident, $TYPE:ident, $CSR:expr) => (
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r!($MOD, $TYPE, $CSR);
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w!($MOD, $TYPE, $CSR);
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||||
)
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}
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macro_rules! csr {
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($MOD:ident, $TYPE:ident, $CSR:expr, $MACRO:ident) => (
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pub struct $TYPE {}
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#[allow(non_upper_case_globals)]
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pub const $MOD: $TYPE = $TYPE {};
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pub mod $MOD {
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$MACRO!($MOD, $TYPE, $CSR);
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}
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)
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}
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/// User Trap Setup
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csr!(ustatus, USTATUS, 0x000, rw);
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csr!(uie, UIE, 0x004, rw);
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csr!(utvec, UTVEC, 0x005, rw);
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/// User Trap Handling
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csr!(uscratch, USCRATCH, 0x040, rw);
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csr!(uepc, UEPC, 0x041, rw);
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csr!(ucause, UCAUSE, 0x042, rw);
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csr!(utval, UTVAL, 0x043, rw);
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csr!(uip, UIP, 0x044, r);
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/// User Floating-Point CSRs
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csr!(fflags, FFLAGS, 0x001, rw);
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csr!(frm, FRM, 0x002, rw);
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csr!(fcsr, FCSR, 0x003, rw);
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/// User Counter/Timers
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csr!(cycle, CYCLE, 0xC00, rw);
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csr!(time, TIME, 0xC01, rw);
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csr!(instret, INSTRET, 0xC02, rw);
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||||
// TODO: hpmcounter3 - hpmcounter31
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csr!(cycleh, CYCLEH, 0xC80, rw);
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csr!(timeh, TIMEH, 0xC81, rw);
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csr!(instreth, INSTRETH, 0xC82, rw);
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// TODO: hpmcounter3h - hpmcounter31h
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/// Supervisor Trap Setup
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csr!(sstatus, SSTATUS, 0x100, rw);
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csr!(sedeleg, SEDELEG, 0x102, rw);
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csr!(sideleg, SIDELEG, 0x103, rw);
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csr!(sie, SIE, 0x104, rw);
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csr!(stvec, STVEC, 0x105, rw);
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csr!(scounteren, SCOUNTEREN, 0x106, rw);
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/// Supervisor Trap Handling
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csr!(sscratch, SSCRATCH, 0x140, rw);
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csr!(sepc, SEPC, 0x141, rw);
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||||
csr!(scause, SCAUSE, 0x142, rw);
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csr!(stval, STVAL, 0x143, rw);
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csr!(sip, SIP, 0x144, r);
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/// Supervisor Protection and Translation
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csr!(satp, SATP, 0x180, rw);
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/// Machine Information Registers
|
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csr!(mvendorid, MVENDORID, 0xF11, r);
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csr!(marchid, MARCHID, 0xF12, r);
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csr!(mimpid, MIMPID, 0xF13, r);
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csr!(mhartid, MHARTID, 0xF14, r);
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/// Machine Trap Setup
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csr!(mstatus, MSTATUS, 0x300, rw);
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csr!(misa, MISA, 0x301, r);
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csr!(medeleg, MEDELEG, 0x302, rw);
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csr!(mideleg, MIDELEG, 0x303, rw);
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csr!(mie, MIE, 0x304, rw);
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csr!(mtvec, MTVEC, 0x305, rw);
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csr!(mcounteren, MCOUNTEREN, 0x306, rw);
|
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/// Machine Trap Handling
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csr!(mscratch, MSCRATCH, 0x340, rw);
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csr!(mepc, MEPC, 0x341, rw);
|
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csr!(mcause, MCAUSE, 0x342, rw);
|
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csr!(mtval, MTVAL, 0x343, rw);
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csr!(mip, MIP, 0x344, r);
|
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/// Machine Protection and Translation
|
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csr!(pmpcfg0, PMPCFG0, 0x3A0, rw);
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csr!(pmpcfg1, PMPCFG1, 0x3A1, rw);
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||||
csr!(pmpcfg2, PMPCFG2, 0x3A2, rw);
|
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csr!(pmpcfg3, PMPCFG3, 0x3A3, rw);
|
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// TODO pmpaddr0 - pmpaddr15
|
||||
|
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/// Machine Counter/Timers
|
||||
csr!(mcycle, MCYCLE, 0xB00, rw);
|
||||
csr!(minstret, MINSTRET, 0xB02, rw);
|
||||
// TODO mhpmcounter3 .. mhpmcounter31
|
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csr!(mcycleh, MCYCLEH, 0xB80, rw);
|
||||
csr!(minstreth, MINSTRETH, 0xB82, rw);
|
||||
// TODO mhpmcounter3h .. mhpmcounter31h
|
||||
/// Machine Counter Setup
|
||||
// TODO mhpmevent3 .. mhpmevent31
|
||||
|
||||
/// Debug/Trace Registers (shared with Debug Mode)
|
||||
csr!(tselect, TSELECT, 0x7A0, rw);
|
||||
csr!(tdata1, TDATA1, 0x7A1, rw);
|
||||
csr!(tdata2, TDATA2, 0x7A2, rw);
|
||||
csr!(tdata3, TDATA3, 0x7A3, rw);
|
||||
/// Debug Mode Registers
|
||||
csr!(dcsr, DCSR, 0x7B0, rw);
|
||||
csr!(dpc, DPC, 0x7B1, rw);
|
||||
csr!(dscratch, DSCRATCH, 0x7B2, rw);
|
||||
|
||||
/// Machine Cause CSR (mcause) is ReadOnly.
|
||||
/// Trap Cause
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub enum Trap {
|
||||
Interrupt(Interrupt),
|
||||
Exception(Exception),
|
||||
}
|
||||
|
||||
/// Interrupt
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub enum Interrupt {
|
||||
UserSoft,
|
||||
SupervisorSoft,
|
||||
MachineSoft,
|
||||
UserTimer,
|
||||
SupervisorTimer,
|
||||
MachineTimer,
|
||||
UserExternal,
|
||||
SupervisorExternal,
|
||||
MachineExternal,
|
||||
}
|
||||
|
||||
impl Interrupt {
|
||||
pub fn from(nr: u32) -> Self {
|
||||
match nr {
|
||||
0 => Interrupt::UserSoft,
|
||||
1 => Interrupt::SupervisorSoft,
|
||||
3 => Interrupt::MachineSoft,
|
||||
4 => Interrupt::UserTimer,
|
||||
5 => Interrupt::SupervisorTimer,
|
||||
7 => Interrupt::MachineTimer,
|
||||
8 => Interrupt::UserExternal,
|
||||
9 => Interrupt::SupervisorExternal,
|
||||
11 => Interrupt::MachineExternal,
|
||||
_ => unreachable!()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Exception
|
||||
#[derive(Copy, Clone, Debug)]
|
||||
pub enum Exception {
|
||||
InstructionMisaligned,
|
||||
InstructionFault,
|
||||
IllegalInstruction,
|
||||
Breakpoint,
|
||||
LoadMisaligned,
|
||||
LoadFault,
|
||||
StoreMisaligned,
|
||||
StoreFault,
|
||||
UserEnvCall,
|
||||
SupervisorEnvCall,
|
||||
MachineEnvCall,
|
||||
InstructionPageFault,
|
||||
LoadPageFault,
|
||||
StorePageFault,
|
||||
}
|
||||
|
||||
impl Exception {
|
||||
pub fn from(nr: u32) -> Self {
|
||||
match nr {
|
||||
0 => Exception::InstructionMisaligned,
|
||||
1 => Exception::InstructionFault,
|
||||
2 => Exception::IllegalInstruction,
|
||||
3 => Exception::Breakpoint,
|
||||
4 => Exception::LoadMisaligned,
|
||||
5 => Exception::LoadFault,
|
||||
6 => Exception::StoreMisaligned,
|
||||
7 => Exception::StoreFault,
|
||||
8 => Exception::UserEnvCall,
|
||||
9 => Exception::SupervisorEnvCall,
|
||||
11 => Exception::MachineEnvCall,
|
||||
12 => Exception::InstructionPageFault,
|
||||
13 => Exception::LoadPageFault,
|
||||
15 => Exception::StorePageFault,
|
||||
_ => unreachable!()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
impl mcause::R {
|
||||
#[inline(always)]
|
||||
/// Trap Cause
|
||||
pub fn cause(&self) -> Trap {
|
||||
let code = self.bits() & !(1 << 31);
|
||||
match self.bits() & (1 << 31) == 1 << 31 {
|
||||
true => Trap::Interrupt(Interrupt::from(code)),
|
||||
false => Trap::Exception(Exception::from(code)),
|
||||
}
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Is trap cause an interrupt.
|
||||
pub fn is_interrupt(&self) -> bool {
|
||||
match self.cause() {
|
||||
Trap::Interrupt(_) => true,
|
||||
_ => false,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Is trap cause an exception.
|
||||
pub fn is_exception(&self) -> bool {
|
||||
match self.cause() {
|
||||
Trap::Exception(_) => true,
|
||||
_ => false,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Machine Status CSR is ReadWrite
|
||||
// TODO: Virtualization, Memory Privilege and Extension Context Fields
|
||||
|
||||
/// Machine Previous Privilege Mode
|
||||
pub enum MPP {
|
||||
Machine = 3,
|
||||
Supervisor = 1,
|
||||
User = 0,
|
||||
}
|
||||
|
||||
/// Supervisor Previous Privilege Mode
|
||||
pub enum SPP {
|
||||
Supervisor = 1,
|
||||
User = 0,
|
||||
}
|
||||
|
||||
|
||||
impl mstatus::R {
|
||||
#[inline(always)]
|
||||
/// User Interrupt Enable
|
||||
pub fn uie(&self) -> bool {
|
||||
self.bits() & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Interrupt Enable
|
||||
pub fn sie(&self) -> bool {
|
||||
self.bits() & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Interrupt Enable
|
||||
pub fn mie(&self) -> bool {
|
||||
self.bits() & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn upie(&self) -> bool {
|
||||
self.bits() & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Previous Interrupt Enable
|
||||
pub fn spie(&self) -> bool {
|
||||
self.bits() & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn mpie(&self) -> bool {
|
||||
self.bits() & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Previous Privilege Mode
|
||||
pub fn spp(&self) -> SPP {
|
||||
match self.bits() & (1 << 8) == (1 << 8) {
|
||||
true => SPP::Supervisor,
|
||||
false => SPP::User,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Previous Privilege Mode
|
||||
pub fn mpp(&self) -> MPP {
|
||||
match (self.bits() & (0b11 << 11)) >> 11 {
|
||||
0b00 => MPP::User,
|
||||
0b01 => MPP::Supervisor,
|
||||
0b11 => MPP::Machine,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl mstatus::W {
|
||||
#[inline(always)]
|
||||
/// User Interrupt Enable
|
||||
pub fn uie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 0)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Interrupt Enable
|
||||
pub fn sie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 1)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Interrupt Enable
|
||||
pub fn mie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 3)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn upie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 4)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn spie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 5)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Previous Interrupt Enable
|
||||
pub fn mpie(&mut self) -> &mut mstatus::W {
|
||||
self.set_bits(1 << 7)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Previous Privilege Mode
|
||||
pub fn spp(&mut self, value: SPP) -> &mut mstatus::W {
|
||||
self.set_bits((value as u32) << 8)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Previous Privilege Mode
|
||||
pub fn mpp(&mut self, value: MPP) -> &mut mstatus::W {
|
||||
self.set_bits((value as u32) << 11)
|
||||
}
|
||||
}
|
||||
|
||||
/// Machine Interrupt Enable CSR (mie) is ReadWrite.
|
||||
impl mie::R {
|
||||
#[inline(always)]
|
||||
/// User Software Interrupt Enable
|
||||
pub fn usoft(&self) -> bool {
|
||||
self.bits() & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Software Interrupt Enable
|
||||
pub fn ssoft(&self) -> bool {
|
||||
self.bits() & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Software Interrupt Enable
|
||||
pub fn msoft(&self) -> bool {
|
||||
self.bits() & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Timer Interrupt Enable
|
||||
pub fn utimer(&self) -> bool {
|
||||
self.bits() & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
pub fn stimer(&self) -> bool {
|
||||
self.bits() & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Timer Interrupt Enable
|
||||
pub fn mtimer(&self) -> bool {
|
||||
self.bits() & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User External Interrupt Enable
|
||||
pub fn uext(&self) -> bool {
|
||||
self.bits() & (1 << 8) == 1 << 8
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor External Interrupt Enable
|
||||
pub fn sext(&self) -> bool {
|
||||
self.bits() & (1 << 9) == 1 << 9
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine External Interrupt Enable
|
||||
pub fn mext(&self) -> bool {
|
||||
self.bits() & (1 << 11) == 1 << 11
|
||||
}
|
||||
}
|
||||
|
||||
impl mie::W {
|
||||
#[inline(always)]
|
||||
/// User Software Interrupt Enable
|
||||
pub fn usoft(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 0)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Software Interrupt Enable
|
||||
pub fn ssoft(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 1)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Software Interrupt Enable
|
||||
pub fn msoft(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 3)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Timer Interrupt Enable
|
||||
pub fn utimer(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 4)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
pub fn stimer(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 5)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Timer Interrupt Enable
|
||||
pub fn mtimer(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 7)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User External Interrupt Enable
|
||||
pub fn uext(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 8)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor External Interrupt Enable
|
||||
pub fn sext(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 9)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine External Interrupt Enable
|
||||
pub fn mext(&mut self) -> &mut mie::W {
|
||||
self.set_bits(1 << 11)
|
||||
}
|
||||
}
|
||||
|
||||
/// Machine Interrupt Pending CSR (mip) is ReadOnly.
|
||||
impl mip::R {
|
||||
#[inline(always)]
|
||||
/// User Software Interrupt Enable
|
||||
pub fn usoft(&self) -> bool {
|
||||
self.bits() & (1 << 0) == 1 << 0
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Software Interrupt Enable
|
||||
pub fn ssoft(&self) -> bool {
|
||||
self.bits() & (1 << 1) == 1 << 1
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Software Interrupt Enable
|
||||
pub fn msoft(&self) -> bool {
|
||||
self.bits() & (1 << 3) == 1 << 3
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User Timer Interrupt Enable
|
||||
pub fn utimer(&self) -> bool {
|
||||
self.bits() & (1 << 4) == 1 << 4
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor Timer Interrupt Enable
|
||||
pub fn stimer(&self) -> bool {
|
||||
self.bits() & (1 << 5) == 1 << 5
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine Timer Interrupt Enable
|
||||
pub fn mtimer(&self) -> bool {
|
||||
self.bits() & (1 << 7) == 1 << 7
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// User External Interrupt Enable
|
||||
pub fn uext(&self) -> bool {
|
||||
self.bits() & (1 << 8) == 1 << 8
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Supervisor External Interrupt Enable
|
||||
pub fn sext(&self) -> bool {
|
||||
self.bits() & (1 << 9) == 1 << 9
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
/// Machine External Interrupt Enable
|
||||
pub fn mext(&self) -> bool {
|
||||
self.bits() & (1 << 11) == 1 << 11
|
||||
}
|
||||
}
|
||||
53
src/interrupt.rs
Normal file
53
src/interrupt.rs
Normal file
@ -0,0 +1,53 @@
|
||||
//! Interrupts
|
||||
|
||||
// NOTE: Adapted from cortex-m/src/interrupt.rs
|
||||
pub use bare_metal::{CriticalSection, Mutex, Nr};
|
||||
|
||||
/// Disables all interrupts
|
||||
#[inline(always)]
|
||||
pub fn disable() {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => ::csr::mstatus.clear(|w| w.mie()),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => {}
|
||||
}
|
||||
}
|
||||
|
||||
/// Enables all the interrupts
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// - Do not call this function inside an `interrupt::free` critical section
|
||||
#[inline(always)]
|
||||
pub unsafe fn enable() {
|
||||
match () {
|
||||
#[cfg(target_arch = "riscv")]
|
||||
() => ::csr::mstatus.set(|w| w.mie()),
|
||||
#[cfg(not(target_arch = "riscv"))]
|
||||
() => {}
|
||||
}
|
||||
}
|
||||
|
||||
/// Execute closure `f` in an interrupt-free context.
|
||||
///
|
||||
/// This as also known as a "critical section".
|
||||
pub fn free<F, R>(f: F) -> R
|
||||
where
|
||||
F: FnOnce(&CriticalSection) -> R,
|
||||
{
|
||||
let mstatus = ::csr::mstatus.read();
|
||||
|
||||
// disable interrupts
|
||||
disable();
|
||||
|
||||
let r = f(unsafe { &CriticalSection::new() });
|
||||
|
||||
// If the interrupts were active before our `disable` call, then re-enable
|
||||
// them. Otherwise, keep them disabled
|
||||
if mstatus.mie() {
|
||||
unsafe { enable() }
|
||||
}
|
||||
|
||||
r
|
||||
}
|
||||
18
src/lib.rs
Normal file
18
src/lib.rs
Normal file
@ -0,0 +1,18 @@
|
||||
//! Low level access to RISCV processors
|
||||
//!
|
||||
//! This crate provides:
|
||||
//!
|
||||
//! - Access to core registers like mstatus or mcause.
|
||||
//! - Interrupt manipulation mechanisms.
|
||||
//! - Safe wrappers around assembly instructions like `mret`.
|
||||
|
||||
#![no_std]
|
||||
#![deny(warnings)]
|
||||
#![feature(asm)]
|
||||
#![feature(const_fn)]
|
||||
|
||||
extern crate bare_metal;
|
||||
|
||||
pub mod asm;
|
||||
pub mod csr;
|
||||
pub mod interrupt;
|
||||
Loading…
Reference in New Issue
Block a user