Vadim Kaushan
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ac1cba597a
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Fix RISC-V name
https://riscv.org/risc-v-trademark-usage/
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2019-01-24 17:19:32 +03:00 |
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Vadim Kaushan
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41378757c0
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Do not require const-fn and asm features
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2019-01-23 01:29:54 +03:00 |
WangRunji
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8776d30d3b
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add S-Mode registers
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
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2018-11-09 22:42:46 +08:00 |
David Craven
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be2a15f34e
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Bump version and update url.
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2018-08-12 08:59:12 +02:00 |
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David Craven
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5e55720ad8
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Update bare-metal.
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2018-08-12 08:59:12 +02:00 |
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David Craven
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34b2ba33cd
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Add inline-asm feature.
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2018-08-12 08:59:12 +02:00 |
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David Craven
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87bcdd8bab
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Bump version.
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2018-04-25 19:43:37 +02:00 |
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David Craven
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7db0e71060
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New api.
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2018-03-27 20:17:44 +02:00 |
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David Craven
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0d9d6cf334
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Bump version to 0.1.4
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2017-11-20 14:23:53 +01:00 |
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David Craven
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b42411e64a
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Bump version to 0.1.3
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2017-11-18 14:10:40 +01:00 |
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David Craven
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1b98011118
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Killing me softly.
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2017-11-18 14:09:53 +01:00 |
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David Craven
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fd78d9bffc
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Bump version to 0.1.2
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2017-11-18 14:05:00 +01:00 |
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David Craven
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94c3b5561e
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Update bare-metal to 0.1.1.
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2017-11-18 14:04:19 +01:00 |
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David Craven
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6ebb6f9790
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Bump version to 0.1.1
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2017-11-18 09:45:01 +01:00 |
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David Craven
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e864581828
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Initial commit.
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2017-09-19 16:23:35 +02:00 |