Vadim Kaushan
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799cdaf6d2
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Fix docs
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2019-03-17 17:28:05 +03:00 |
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Vadim Kaushan
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16fdb16730
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Update docs
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2019-01-24 17:20:23 +03:00 |
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Vadim Kaushan
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ac1cba597a
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Fix RISC-V name
https://riscv.org/risc-v-trademark-usage/
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2019-01-24 17:19:32 +03:00 |
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Vadim Kaushan
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41378757c0
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Do not require const-fn and asm features
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2019-01-23 01:29:54 +03:00 |
WangRunji
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8776d30d3b
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add S-Mode registers
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
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2018-11-09 22:42:46 +08:00 |
David Craven
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7db0e71060
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New api.
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2018-03-27 20:17:44 +02:00 |
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David Craven
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e864581828
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Initial commit.
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2017-09-19 16:23:35 +02:00 |