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135 Commits

Author SHA1 Message Date
Vadim Kaushan 496120e89f
Add debug info, strip prefix 2020-06-14 14:53:38 +03:00
Vadim Kaushan e21ce5249f
Remove write functions for read-only registers 2020-06-14 14:45:17 +03:00
Vadim Kaushan 707f51f46e
Fix docs 2020-06-14 14:45:10 +03:00
Vadim Kaushan 426fc067b4
Allow unused macros 2020-06-14 14:45:02 +03:00
Vadim Kaushan 7ce847ee3c
Fix register docs 2020-06-14 14:44:16 +03:00
Vadim Kaushan a131c16360
Remove unused dependencies 2020-06-14 14:22:50 +03:00
Vadim Kaushan a9b4b7149f
Regenerate binaries 2020-06-14 14:22:08 +03:00
Vadim Kaushan 11e7118729
Remove all the RISC-V standard registers 2020-06-14 14:20:38 +03:00
Vadim Kaushan b4546d1827
Remove asm and interrupt modules 2020-06-14 14:17:55 +03:00
Vadim Kaushan 9bf5caafc2
Remove #![deny(warnings)] (anti-pattern) 2020-06-14 14:16:26 +03:00
Vadim Kaushan 18995feba8
Revert "README: Obsolete" 
This reverts commit b7befcf608.
 2020-06-14 14:06:04 +03:00
Sean Cross b7befcf608
README: Obsolete 2020-03-18 23:36:30 +08:00
Sean Cross 5846f57ab1 cargo: bump version to 0.0.2 
This version adds vexriscv-specific registers.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-01-08 17:23:05 +08:00
Sean Cross fd54453416 register: add vexriscv-specific registers 
Vexriscv in its normal configuration has its own registers for things
such as machine interrupts and system interrupts.  Add wrappers for
these registers.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-01-08 17:22:16 +08:00
Sean Cross 8bc0b06f95 bin: update name of object file 
This minor update simply changes the name of the object file within the
library.  It should have no user-facing changes.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-12-28 18:29:06 +08:00
Sean Cross 5121f28fde cargo: remove `vexriscv` category 
Apparently categories are fixed, and vexriscv isn't a category.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-12-28 18:14:52 +08:00
Sean Cross 28ded4136a vexriscv: clone from riscv crate 
Base the vexriscv crate on the riscv crate, but add vexriscv-specific
instructions.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-12-28 18:12:31 +08:00
bors[bot] 0259333c75
Merge #34 
34: mip, satp: Allow writing to these privileged registers r=laanwj a=archshift

Per the RISC-V privileged ISA, these registers should be writable.

Co-authored-by: Gui Andrade <gh@archshift.com>
 2019-10-10 07:32:26 +00:00
Gui Andrade 7a9aa062a0 Allow writing directly to satp register 2019-10-08 18:10:38 -07:00
Gui Andrade 95c52341c4 mip: Add set/clear functions for bits 2019-10-08 17:57:29 -07:00
bors[bot] 0eda3c511c
Merge #32 
32: add user trap setup and handling registers r=almindor a=almindor

Adds CSR handlers for user trap setup and handling registers.

Also unifies common shared types.

NOTE: untested, will test on real device ASAP

Co-authored-by: Ales Katona <almindor@gmail.com>
 2019-09-13 21:15:02 +00:00
Ales Katona 73f45e3dbf
Merge branch 'master' into ustatus 2019-09-13 11:21:44 -06:00
bors[bot] 9d68612325
Merge #33 
33: Do not use bare-metal v0.2.5 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-09-13 01:06:16 +00:00
Vadim Kaushan b834ae45a5
Do not use bare-metal v0.2.5 (changes MSRV) 2019-09-05 19:53:02 +03:00
Ales Katona 8840aee369
ucause only as readable bits 2019-08-31 17:32:43 -06:00
Ales Katona e1232ed680
clean up formatting 2019-08-31 16:12:39 -06:00
Ales Katona cdf6a33665
remove XS and FS from ustatus 2019-08-31 16:10:56 -06:00
Ales Katona 13831f7a80
revert scause specific trap/exceptions 2019-08-31 16:09:47 -06:00
Ales Katona f443bcf698
remove invalid comment 2019-08-28 09:26:02 -06:00
Ales Katona 30555e4d79
fix typos in asm calls 2019-08-27 09:47:57 -06:00
Ales Katona 49446ad869
fix ustatus doc typos 2019-08-27 09:46:14 -06:00
Ales Katona 2180ef44d5
add user trap setup and handling registers 2019-08-27 09:40:47 -06:00
bors[bot] 4094a32f43 Merge #30 
30: add riscv32i target r=Disasm a=sbourdeauducq

This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with  FPGA softcore implementations.

Co-authored-by: Sebastien Bourdeauducq <sb@m-labs.hk>
 2019-07-27 12:59:37 +00:00
Sebastien Bourdeauducq b53e0a5cd2 add riscv32i target 2019-07-26 00:13:38 +08:00
bors[bot] 7f1e4a56cf Merge #31 
31: Add more CSRs r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-07-23 17:41:40 +00:00
Vadim Kaushan d3dc245ce4
Bump version (0.5.4) 2019-07-03 01:37:34 +03:00
Vadim Kaushan 31f4127702
Add PMP CSRs 2019-06-26 11:25:45 +03:00
Vadim Kaushan f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs 2019-06-26 00:51:37 +03:00
Vadim Kaushan 298a8b6f6e
Provide write() for mepc 2019-06-25 23:48:47 +03:00
Vadim Kaushan 7a8d3d1f6c
Implement mscratch and mtval registers 2019-06-25 23:48:27 +03:00
Vadim Kaushan 00367d4fd2
Add sections to the registers module 2019-06-25 23:34:47 +03:00
Vadim Kaushan 370a654d2c
Regenerate binaries 2019-06-25 23:34:20 +03:00
Vadim Kaushan a659a0cc39
Declare all the CSR registers in asm.S 2019-06-25 23:33:40 +03:00
Vadim Kaushan ac2ac6756b
Derive useful traits for enums 2019-06-25 23:32:51 +03:00
bors[bot] 5a1ab837b4 Merge #28 
28: Add marchid, mhartid and mimpid registers r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-06-25 19:40:12 +00:00
Vadim Kaushan 2965734b7b
Bump version (0.5.3) 2019-04-29 10:45:19 +02:00
Vadim Kaushan 2ef11206bd
Regenerate binaries 2019-04-29 10:44:45 +02:00
Vadim Kaushan cf9008492a
Add marchid, mhartid and mimpid registers 2019-04-29 10:43:51 +02:00
bors[bot] 1e514648fd Merge #26 
26: Fix Misa::has_extension() r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-04-01 19:06:47 +00:00
Vadim Kaushan c3ff23989e
Bump version (0.5.2) 2019-04-01 19:59:10 +03:00