vexriscv-rust/src/lib.rs

28 lines
765 B
Rust
Raw Normal View History

//! Low level access to RISC-V processors
2017-09-19 22:04:12 +08:00
//!
2019-03-17 22:29:48 +08:00
//! # Minimum Supported Rust Version (MSRV)
//!
//! This crate is guaranteed to compile on stable Rust 1.30 and up. It *might*
//! compile with older versions but that may change in any new patch release.
//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
//! are not supported on stable yet.
//!
//! # Features
//!
2017-09-19 22:04:12 +08:00
//! This crate provides:
//!
2019-03-17 22:28:05 +08:00
//! - Access to core registers like `mstatus` or `mcause`.
2017-09-19 22:04:12 +08:00
//! - Interrupt manipulation mechanisms.
2019-01-24 22:20:23 +08:00
//! - Wrappers around assembly instructions like `WFI`.
2017-09-19 22:04:12 +08:00
#![no_std]
#![deny(warnings)]
#![cfg_attr(feature = "inline-asm", feature(asm))]
2017-09-19 22:04:12 +08:00
extern crate bare_metal;
extern crate bit_field;
2017-09-19 22:04:12 +08:00
pub mod asm;
pub mod interrupt;
2018-03-28 02:17:44 +08:00
pub mod register;