vexriscv-rust/src/lib.rs

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2017-09-19 22:04:12 +08:00
//! Low level access to RISCV processors
//!
//! This crate provides:
//!
//! - Access to core registers like mstatus or mcause.
//! - Interrupt manipulation mechanisms.
//! - Safe wrappers around assembly instructions like `mret`.
#![no_std]
#![deny(warnings)]
#![feature(asm)]
#![feature(const_fn)]
extern crate bare_metal;
pub mod asm;
pub mod csr;
pub mod interrupt;