development setup

README.md

@@ -28,6 +28,10 @@ Notes:
 
 - The impure build process is also compatible with non-Nix systems.
 - If the board is connected to the local machine, use the ``local_run.sh`` script.
+- Due to questionable Zynq design decisions, JTAG boot works only once per power cycle.
+  A good workaround is to power the Red Pitaya through a uhubctl-compatible USB hub and
+  boot with a command such as:
+  ``ssh rpi-3.m-labs.hk "uhubctl -a off -p 4; sleep 2; uhubctl -a on -p 4; sleep 2" && ./remote_run.sh -i``
 
 License
 -------

remote_run.sh

@@ -11,7 +11,7 @@ if [ -z "$SZL" ]; then
     exit 1
 fi
 
-target_host="rpi-4.m-labs.hk"
+target_host="rpi-3.m-labs.hk"
 impure=0
 pure_dir="result"
 impure_dir="build"

src/firmware/src/main.rs

@@ -5,11 +5,23 @@ extern crate alloc;
 
 use core::{cmp, str};
 use log::{info, warn};
+use alloc::vec;
 
 use libcortex_a9::{asm, cache};
-use libboard_zynq::{timer::GlobalTimer, logger, slcr};
+use libboard_zynq::{
+    eth::Eth,
+    smoltcp::{
+        self,
+        iface::{EthernetInterfaceBuilder, NeighborCache},
+        time::Instant,
+        wire::IpCidr,
+    },
+    timer::GlobalTimer,
+    logger,
+    slcr
+};
+use libconfig::{net_settings, Config};
 use libsupport_zynq::ram;
-use libconfig::Config;
 use libregister::RegisterW;
 
 #[path = "../../../build/pl.rs"]
@@ -52,7 +64,7 @@ fn identifier_read(buf: &mut [u8]) -> &str {
 }
 
 
-const BUFFER_SIZE: usize = 128;
+const BUFFER_SIZE: usize = 16*1024*1024;
 
 #[repr(C, align(128))]
 struct DmaBuffer {
@@ -61,6 +73,40 @@ struct DmaBuffer {
 
 static mut BUFFER: DmaBuffer = DmaBuffer { data: [0; BUFFER_SIZE] };
 
+
+fn start_sampling() {
+    unsafe {
+        let base_addr = &mut BUFFER.data[0] as *mut _ as usize;
+        pl::csr::adc::base_address_write(base_addr as u32);
+        pl::csr::adc::length_write(BUFFER_SIZE as u32);
+
+        cache::dcci_slice(&BUFFER.data);
+        pl::csr::adc::start_write(1);
+    }
+}
+
+fn sampling_done() -> bool {
+    unsafe {
+        let busy = pl::csr::adc::busy_read();
+        if busy == 0 {
+            info!("done, bus_error={}, overflow={}",
+                pl::csr::adc::bus_error_read(), pl::csr::adc::overflow_read());
+            cache::dcci_slice(&BUFFER.data);
+            true
+        } else {
+            false
+        }
+    }
+}
+
+#[derive(PartialEq)]
+enum State {
+    Idle,
+    Sampling,
+    SamplingAbort,
+    Transfer(usize)
+}
+
 #[no_mangle]
 pub fn main_core0() {
     GlobalTimer::start();
@@ -82,27 +128,96 @@ pub fn main_core0() {
         }
     };
 
-    unsafe {
-        let base_addr = &mut BUFFER.data[0] as *mut _ as usize;
-        pl::csr::adc::base_address_write(base_addr as u32);
-        pl::csr::adc::length_write(BUFFER_SIZE as u32);
+    let net_addresses = net_settings::get_addresses(&cfg);
+    log::info!("Network addresses: {}", net_addresses);
+    let eth = Eth::eth0(net_addresses.hardware_addr.0.clone());
+    let eth = eth.start_rx(8);
+    let mut eth = eth.start_tx(8);
 
-        cache::dcci_slice(&BUFFER.data);
-        pl::csr::adc::start_write(1);
+    let mut neighbor_map = [None; 2];
+    let neighbor_cache = NeighborCache::new(&mut neighbor_map[..]);
+    let mut ip_addrs = [IpCidr::new(net_addresses.ipv4_addr, 0)];
+    let mut interface = EthernetInterfaceBuilder::new(&mut eth)
+        .ethernet_addr(net_addresses.hardware_addr)
+        .ip_addrs(&mut ip_addrs[..])
+        .neighbor_cache(neighbor_cache)
+        .finalize();
 
-        let busy = pl::csr::adc::busy_read();
-        info!("started {}", busy);
-        while pl::csr::adc::busy_read() != 0 {}
-        info!("done, bus_error={}, overflow={}",
-            pl::csr::adc::bus_error_read(), pl::csr::adc::overflow_read());
-        cache::dcci_slice(&BUFFER.data);
-        for i in 0..BUFFER_SIZE {
-            info!("{:02x}", BUFFER.data[i]);
-        }
-    }
+    let mut rx_storage = vec![0; 64];
+    let mut tx_storage = vec![0; 4096];
 
+    let mut socket_set_entries: [_; 1] = Default::default();
+    let mut sockets = smoltcp::socket::SocketSet::new(&mut socket_set_entries[..]);
+
+    let tcp_rx_buffer = smoltcp::socket::TcpSocketBuffer::new(&mut rx_storage[..]);
+    let tcp_tx_buffer = smoltcp::socket::TcpSocketBuffer::new(&mut tx_storage[..]);
+    let tcp_socket = smoltcp::socket::TcpSocket::new(tcp_rx_buffer, tcp_tx_buffer);
+    let tcp_handle = sockets.add(tcp_socket);
+
+    let timer = unsafe { GlobalTimer::get() };
+    let mut state = State::Idle;
+
+    log::info!("Waiting for connections...");
     loop {
-        asm::wfe();
+        let timestamp = Instant::from_millis(timer.get_time().0 as i64);
+        {
+            let socket = &mut *sockets.get::<smoltcp::socket::TcpSocket>(tcp_handle);
+
+            if !socket.is_open() {
+                socket.listen(1550).unwrap();
+            }
+
+            if socket.may_recv() {
+                let start_cmd = socket.recv(|data| (data.len(), data.len() > 0)).unwrap();
+                if start_cmd && state == State::Idle {
+                    log::info!("start sampling");
+                    start_sampling();
+                    state = State::Sampling;
+                }
+            } else if socket.may_send() {
+                log::info!("disconnected");
+                if state == State::Sampling {
+                    state = State::SamplingAbort;
+                } else {
+                    state = State::Idle;
+                }
+                socket.close();
+            }
+
+            if state == State::SamplingAbort {
+                if sampling_done() {
+                    state = State::Idle;
+                }
+            }
+            if state == State::Sampling {
+                if sampling_done() {
+                    state = State::Transfer(0);
+                }
+            }
+            if let State::Transfer(done) = state {
+                match socket.send_slice(unsafe { &BUFFER.data[done..] }) {
+                    Ok(just_sent) => {
+                        let done = done + just_sent;
+                        if done == BUFFER_SIZE {
+                            state = State::Idle;
+                        } else {
+                            state = State::Transfer(done);
+                        }
+                    }
+                    Err(e) => {
+                        log::error!("error while transmitting: {}", e);
+                        state = State::Idle;
+                        socket.close();
+                    }
+                }
+            }
+        }
+
+        match interface.poll(&mut sockets, timestamp) {
+            Ok(_) => (),
+            Err(smoltcp::Error::Unrecognized) => (),
+            Err(err) => log::error!("Network error: {}", err),
+        }
     }
 }
 

src/gateware/dma.py

@@ -1,6 +1,6 @@
 from migen import *
 from migen.genlib.fsm import FSM
-from migen.genlib.fifo import SyncFIFOBuffered
+from migen.genlib.fifo import SyncFIFO
 from migen_axi.interconnect import axi
 from misoc.interconnect.csr import *
 
@@ -69,7 +69,7 @@ class ADCWriter(Module):
         self.overflow = Signal()
         self.busy = Signal()
 
-        fifo = SyncFIFOBuffered(64, 512)
+        fifo = SyncFIFO(64, 32, fwft=True)
         self.submodules += fifo
 
         # FIFO write
@@ -95,10 +95,10 @@ class ADCWriter(Module):
         assert AXI_DATA_WIDTH == len(fifo_inbuf)
         remaining = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8)) # in AXI_DATA_WIDTH words
         self.sync += [
-            If(remaining != 0, remaining.eq(remaining - 1)),
+            If(fifo.we & fifo.writable, remaining.eq(remaining - 1)),
             If(self.start, remaining.eq(self.length << log2_int(AXI_BURST_LEN))),
         ]
-        self.comb += fifo.we.eq((remaining != 0) & ~fifo_inbuf_sel)
+        self.comb += fifo.we.eq((remaining != 0) & fifo_inbuf_sel)
 
         self.comb += self.overflow.eq(fifo.we & ~fifo.writable)
 
@@ -123,13 +123,7 @@ class ADCWriter(Module):
             )
         ]
 
-        # Busy generation
-        remaining_sys = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8))
-        self.sync += [
-           If(self.start, remaining_sys.eq(self.length << log2_int(AXI_BURST_LEN))),
-           If(fifo.readable & fifo.re, remaining_sys.eq(remaining_sys - 1))
-        ]
-        self.comb += self.busy.eq(remaining_sys != 0)
+        self.comb += self.busy.eq((remaining != 0) | fifo.readable)
 
 
 class ADC(Module, AutoCSR):

src/gateware/rust-pitaya.py

@@ -22,7 +22,7 @@ class RustPitaya(SoCCore):
         ident = self.__class__.__name__
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
 
-        # CLock everything from the ADC clock
+        # Clock everything from the ADC clock
         clk125_pads = platform.request("clk125")
         platform.add_platform_command("create_clock -name clk_sys -period 8 [get_ports {port}]", port=clk125_pads.p)
         self.clock_domains.cd_sys = ClockDomain(reset_less=True)