Reduce lane count to 4 for easier debugging

2020-10-20 11:40:19 +08:00 · 2020-10-20 11:40:19 +08:00 · b9481cecf5
parent 577a8083f1
commit b9481cecf5
1 changed files with 1 additions and 1 deletions
--- a/rtio/test/sed/output_network.py
+++ b/rtio/test/sed/output_network.py
@ -11,7 +11,7 @@ class OutputNetworkTestCase(FHDLTestCase):
    def verify(self):
        # Bounded model check
        self.assertFormal(
-            OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True),
+            OutputNetwork(4, 2, [("data", 32), ("channel", 3)], fv_mode=True),
            mode="bmc", depth=40)
        # TODO: unbounded proof