From b9481cecf5a80e31521c86f760b40adb7bb9479d Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Tue, 20 Oct 2020 11:40:19 +0800
Subject: [PATCH] Reduce lane count to 4 for easier debugging

---
 rtio/test/sed/output_network.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtio/test/sed/output_network.py b/rtio/test/sed/output_network.py
index deb2317..9e4cd6c 100644
--- a/rtio/test/sed/output_network.py
+++ b/rtio/test/sed/output_network.py
@@ -11,7 +11,7 @@ class OutputNetworkTestCase(FHDLTestCase):
     def verify(self):
         # Bounded model check
         self.assertFormal(
-            OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True),
+            OutputNetwork(4, 2, [("data", 32), ("channel", 3)], fv_mode=True),
             mode="bmc", depth=40)
         # TODO: unbounded proof