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Reduce lane count to 4 for easier debugging

This commit is contained in:
Donald Sebastian Leung 2020-10-20 11:40:19 +08:00
parent 577a8083f1
commit b9481cecf5
1 changed files with 1 additions and 1 deletions
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2
rtio/test/sed/output_network.py
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@ -11,7 +11,7 @@ class OutputNetworkTestCase(FHDLTestCase):
def verify(self): def verify(self):
# Bounded model check # Bounded model check
self.assertFormal( self.assertFormal(
OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True), OutputNetwork(4, 2, [("data", 32), ("channel", 3)], fv_mode=True),
mode="bmc", depth=40) mode="bmc", depth=40)
# TODO: unbounded proof # TODO: unbounded proof