From 8fe67cf6f48582094319e2827c1361bbe49456f2 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Mon, 19 Oct 2020 12:39:32 +0800
Subject: [PATCH] Skip assertions for configurable no. of clock cycles
---
rtio/sed/output_network.py | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/rtio/sed/output_network.py b/rtio/sed/output_network.py
index dfa3c1c..0f03e97 100644
--- a/rtio/sed/output_network.py
+++ b/rtio/sed/output_network.py
@@ -119,8 +119,16 @@ class OutputNetwork(Elaboratable):
f_past_valid = Signal()
m.d.sync += f_past_valid.eq(1)
+ # Skip assertions for the first 10 time steps
+ counter = Signal(4)
+ m.d.sync += counter.eq(counter + 1)
+ with m.If(counter >= 10):
+ m.d.sync += counter.eq(counter)
+ f_past10_valid = Signal()
+ m.d.comb += f_past10_valid.eq(counter >= 10)
+
# Valid nodes always come first in outputs
- with m.If(f_past_valid):
+ with m.If(f_past10_valid):
for i in range(lane_count - 1):
m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing