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Increase BMC depth for sorting network assertions

pull/1/head
Donald Sebastian Leung 2020-10-16 13:41:38 +08:00
parent 036c91539b
commit 5011245007
2 changed files with 4 additions and 6 deletions
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8
rtio/sed/output_network.py
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@ -119,12 +119,10 @@ class OutputNetwork(Elaboratable):
f_past_valid = Signal() f_past_valid = Signal()
m.d.sync += f_past_valid.eq(1) m.d.sync += f_past_valid.eq(1)
# TODO: assert outputs is a permutation of inputs # Valid nodes always come first in outputs
# Channel numbers for outputs are sorted in increasing order
with m.If(f_past_valid): with m.If(f_past_valid):
# TODO: Get the below (bogus) assertion to fail for i in range(lane_count - 1):
m.d.comb += Assert(self.output[7].payload.channel == 0) m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing
def elaborate(self, platform): def elaborate(self, platform):
return self.m return self.m

2
rtio/test/sed/output_network.py
View File

@ -12,7 +12,7 @@ class OutputNetworkTestCase(FHDLTestCase):
# Bounded model check # Bounded model check
self.assertFormal( self.assertFormal(
OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True), OutputNetwork(16, 2, [("data", 32), ("channel", 3)], fv_mode=True),
mode="bmc", depth=10) mode="bmc", depth=40)
# TODO: unbounded proof # TODO: unbounded proof
OutputNetworkTestCase().verify() OutputNetworkTestCase().verify()