2020-09-23 17:10:41 +08:00
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# rtio-nmigen
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2020-09-23 17:14:27 +08:00
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Formally verified implementation of the ARTIQ RTIO core in nMigen
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## Progress
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- [ ] Implement the core in nMigen
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2020-09-24 15:43:33 +08:00
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- - [ ] `artiq.gateware.rtio.core`
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- - [ ] `misoc.interconnect.csr`
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- - [ ] `artiq.gateware.rtio.cri`
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2020-09-25 12:49:14 +08:00
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- - [x] `artiq.gateware.rtio.rtlink`
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2020-09-25 12:59:23 +08:00
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- - [x] `artiq.gateware.rtio.channel`
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2020-09-24 15:43:33 +08:00
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- - [ ] `artiq.gateware.rtio.sed.core`
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2020-09-25 13:26:01 +08:00
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- - [x] `artiq.gateware.rtio.sed.layouts`
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2020-09-24 15:43:33 +08:00
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- - [ ] `artiq.gateware.rtio.sed.lane_distributor`
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- - [ ] `artiq.gateware.rtio.sed.fifos`
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- - [ ] `artiq.gateware.rtio.sed.gates`
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- - [ ] `artiq.gateware.rtio.sed.output_driver`
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- - [ ] `artiq.gateware.rtio.sed.output_network`
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- - [ ] `artiq.gateware.rtio.input_collector`
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2020-09-23 17:14:27 +08:00
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- [ ] Add suitable assertions for verification (BMC / unbounded proof?)
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## License
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Copyright (C) 2020 M-Labs Limited.
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2020-09-23 17:16:58 +08:00
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[LGPLv3](./LICENSE) or any later version
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