rtio-nmigen/README.md

28 lines
824 B
Markdown
Raw Normal View History

2020-09-23 17:10:41 +08:00
# rtio-nmigen
2020-09-23 17:14:27 +08:00
Formally verified implementation of the ARTIQ RTIO core in nMigen
## Progress
- [ ] Implement the core in nMigen
2020-09-24 15:43:33 +08:00
- - [ ] `artiq.gateware.rtio.core`
- - [ ] `misoc.interconnect.csr`
- - [ ] `artiq.gateware.rtio.cri`
- - [ ] `artiq.gateware.rtio.rtlink`
- - [ ] `artiq.gateware.rtio.channel`
- - [ ] `artiq.gateware.rtio.sed.core`
- - [ ] `artiq.gateware.rtio.sed.layouts`
- - [ ] `artiq.gateware.rtio.sed.lane_distributor`
- - [ ] `artiq.gateware.rtio.sed.fifos`
- - [ ] `artiq.gateware.rtio.sed.gates`
- - [ ] `artiq.gateware.rtio.sed.output_driver`
- - [ ] `artiq.gateware.rtio.sed.output_network`
- - [ ] `artiq.gateware.rtio.input_collector`
2020-09-23 17:14:27 +08:00
- [ ] Add suitable assertions for verification (BMC / unbounded proof?)
## License
Copyright (C) 2020 M-Labs Limited.
2020-09-23 17:16:58 +08:00
[LGPLv3](./LICENSE) or any later version