Commit Graph

79 Commits

Author SHA1 Message Date
e24ddd4269 Fix LUI instruction 2020-07-30 16:07:47 +08:00
9974db7e7b Refactor BGEU instruction 2020-07-30 15:53:39 +08:00
331cfda279 Refactor BLTU instruction 2020-07-30 15:49:56 +08:00
847099e4de Refactor BGE instruction 2020-07-30 15:46:18 +08:00
583d165ec1 Refactor BLT instruction 2020-07-30 15:42:10 +08:00
31f6847640 Refactor BNE instruction 2020-07-30 14:14:24 +08:00
3d1bb14bae Refactor BEQ instruction 2020-07-30 14:10:48 +08:00
4a695c950d Add SB-type instruction format 2020-07-30 14:03:59 +08:00
f4f5e94843 Refactor JALR instruction 2020-07-30 13:56:30 +08:00
e6c6f0462e Add I-type instruction format 2020-07-30 13:48:01 +08:00
7846ba95ac Refactor JAL instruction 2020-07-30 13:34:52 +08:00
a84b6d50b8 Add UJ-type instruction format 2020-07-30 13:15:17 +08:00
3dc2a174fd Refactor AUIPC instruction 2020-07-30 13:01:13 +08:00
927c12e97c Refactor LUI instruction 2020-07-30 12:55:57 +08:00
34c8b6cf3d Create U-type instruction format 2020-07-30 12:45:32 +08:00
c9c47ddc35 Create general instruction class 2020-07-30 12:06:51 +08:00
2421f1f6b6 Add RV32IM ISA 2020-07-24 13:51:04 +08:00
5bce84836c Add REMU instruction for RV32M 2020-07-24 13:32:43 +08:00
4600eaeb74 Add REM instruction for RV32M 2020-07-24 13:30:06 +08:00
7f3f88cb69 Add DIVU instruction for RV32M 2020-07-24 13:27:48 +08:00
2b198303c6 Add DIV instruction for RV32M 2020-07-24 13:25:17 +08:00
f13208455d Add MULHU instruction for RV32M 2020-07-24 13:22:41 +08:00
7a61919a88 Add MULHSU instruction for RV32M 2020-07-24 13:20:05 +08:00
9b4f6ac359 Add MULH instruction for RV32M 2020-07-24 13:16:47 +08:00
c72205d433 Modify MUL instruction to use alternative operations 2020-07-24 13:13:03 +08:00
dec39cb11d Re-add MUL instruction 2020-07-24 12:55:11 +08:00
f33d229b2c Fix XOR instruction 2020-07-24 12:49:33 +08:00
d54269d3f0 Fix SUB instruction 2020-07-24 12:48:08 +08:00
fe2ff5150a Fix SRL instruction 2020-07-24 12:46:24 +08:00
6d35ecdc80 Fix SRA instruction 2020-07-24 12:44:44 +08:00
3c1510ebbc Fix SLT instruction 2020-07-24 12:42:27 +08:00
18e43d9689 Fix SLL instruction 2020-07-24 12:40:28 +08:00
d59ebda628 Fix OR instruction 2020-07-24 12:32:59 +08:00
3028246b73 Fix AND instruction 2020-07-24 12:24:43 +08:00
eedfc843f7 Fix ADD instruction 2020-07-24 12:21:07 +08:00
73005eb3c3 Revert MUL instruction 2020-07-24 12:17:02 +08:00
14c87fdde2 Add MUL instruction for RV32M 2020-07-24 12:13:40 +08:00
35a53071aa Complete generator for RV32I ISA 2020-07-23 14:33:25 +08:00
2e7cc106aa Add missing return in ports in RV32I ISA 2020-07-23 12:57:32 +08:00
badd480a45 Prepare generator script for RV32I ISA 2020-07-23 12:42:59 +08:00
d54a60879d Add list of supported instructions for RV32I 2020-07-23 11:18:41 +08:00
61393b9a4f Add AND instruction for RV32I 2020-07-22 16:39:08 +08:00
93978ccdb4 Add OR instruction for RV32I 2020-07-22 16:36:40 +08:00
4eae7064fb Add SRA instruction for RV32I 2020-07-22 16:32:51 +08:00
ada2a09818 Add SRL instruction for RV32I 2020-07-22 16:16:27 +08:00
192aec2347 Add XOR instruction for RV32I 2020-07-22 16:11:58 +08:00
c6c18765f5 Add SLTU instruction for RV32I 2020-07-22 16:08:09 +08:00
adcf7dc4ab Add SLT instruction for RV32I 2020-07-22 16:04:47 +08:00
728e24b0df Add SLL instruction for RV32I 2020-07-22 16:00:46 +08:00
6940574d73 Add SUB instruction for RV32I 2020-07-22 15:55:44 +08:00