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riscv-formal-nmigen
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Explicitly define reset value in cycle signal for uniqueness check

This commit is contained in:
Donald Sebastian Leung 2020-09-17 13:25:52 +08:00
parent 32388adce0
commit c4cbc4bfea
1 changed files with 1 additions and 1 deletions
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2
rvfi/cores/minerva/verify.py
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@ -555,7 +555,7 @@ class UniqueSpec(Elaboratable):
m.d.comb += cpu.dbus.ack.eq(AnySeq(1)) m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
m.d.comb += cpu.dbus.err.eq(0) m.d.comb += cpu.dbus.err.eq(0)
cycle = Signal(8) cycle = Signal(8, reset=0)
with m.If(cycle != 0xFF): with m.If(cycle != 0xFF):
m.d.sync += cycle.eq(cycle + 1) m.d.sync += cycle.eq(cycle + 1)
m.d.comb += unique_spec.reset.eq(cycle < 1) m.d.comb += unique_spec.reset.eq(cycle < 1)