M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
363 Commits 1 Branch 0 Tags 683 KiB
Python 99.4%
Nix 0.6%
Go to file
Donald Sebastian Leung c4cbc4bfea Explicitly define reset value in cycle signal for uniqueness check 2020-09-17 13:25:52 +08:00
rvfi Explicitly define reset value in cycle signal for uniqueness check 2020-09-17 13:25:52 +08:00
LICENSE Fix copyright holder in license 2020-08-03 12:19:14 +08:00
README.md Make liveness checks pass 2020-09-17 13:22:52 +08:00
shell.nix Remove copy of Minerva 2020-08-20 15:32:10 +08:00

README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

File/Directory Description
shell.nix nix-shell configuration file
rvfi RISC-V Formal Verification Framework (nMigen port)
rvfi/insns Supported RISC-V instructions and ISAs
rvfi/checks Checks for RISC-V compliant cores
rvfi/cores Cores currently tested against this port of riscv-formal
rvfi/cores/minerva/verify.py Verification tasks for the Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:

$ python -m rvfi.cores.minerva.verify

This should run in the order of a few hours.

Progress

  • Instruction Checks
  • PC forward checks
  • PC backward checks
  • Register checks
  • Causal checks
  • Liveness checks
  • Uniqueness checks

Scope

The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM are being tested by integrating with the Minerva core.

License

See LICENSE