From c4cbc4bfea33758a5d3ae5110ffc637aec5fcc1f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 17 Sep 2020 13:25:52 +0800 Subject: [PATCH] Explicitly define reset value in cycle signal for uniqueness check --- rvfi/cores/minerva/verify.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rvfi/cores/minerva/verify.py b/rvfi/cores/minerva/verify.py index d2dede2..ac1d561 100644 --- a/rvfi/cores/minerva/verify.py +++ b/rvfi/cores/minerva/verify.py @@ -555,7 +555,7 @@ class UniqueSpec(Elaboratable): m.d.comb += cpu.dbus.ack.eq(AnySeq(1)) m.d.comb += cpu.dbus.err.eq(0) - cycle = Signal(8) + cycle = Signal(8, reset=0) with m.If(cycle != 0xFF): m.d.sync += cycle.eq(cycle + 1) m.d.comb += unique_spec.reset.eq(cycle < 1)