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Add RV32I I-Type Instruction (Shift Variation)

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Donald Sebastian Leung 2020-08-07 16:39:14 +08:00
parent 1c0541cd12
commit 9e64c7ee17
1 changed files with 26 additions and 0 deletions
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insns/InsnRV32IITypeShift.py Normal file
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from Insn import *
"""
RV32I I-Type Instruction (Shift Variation)
"""
class InsnRV32IITypeShift(Insn):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct6, funct3):
super(InsnRV32IITypeShift, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
self.funct6 = funct6
self.funct3 = funct3
def elaborate(self, platform):
m = super(InsnRV32IITypeShift, self).elaborate(platform)
if self.RISCV_FORMAL_CSR_MISA:
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
m.d.comb += self.spec_csr_misa_rmask.eq(0)
else:
m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
return m