From 9e64c7ee176d1681284b0c5b437d1e865c9e88cb Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 16:39:14 +0800 Subject: [PATCH] Add RV32I I-Type Instruction (Shift Variation) --- insns/InsnRV32IITypeShift.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 insns/InsnRV32IITypeShift.py diff --git a/insns/InsnRV32IITypeShift.py b/insns/InsnRV32IITypeShift.py new file mode 100644 index 0000000..ab28f2c --- /dev/null +++ b/insns/InsnRV32IITypeShift.py @@ -0,0 +1,26 @@ +from Insn import * + +""" +RV32I I-Type Instruction (Shift Variation) +""" + +class InsnRV32IITypeShift(Insn): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct6, funct3): + super(InsnRV32IITypeShift, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + self.funct6 = funct6 + self.funct3 = funct3 + def elaborate(self, platform): + m = super(InsnRV32IITypeShift, self).elaborate(platform) + + if self.RISCV_FORMAL_CSR_MISA: + m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) + m.d.comb += self.spec_csr_misa_rmask.eq(0) + else: + m.d.comb += self.misa_ok.eq(1) + + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m