Prepare RV32I Base ISA
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# Generated by IsaRV32IGen.py
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from InsnLui import *
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from InsnAuipc import *
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from InsnJal import *
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from InsnJalr import *
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from InsnBeq import *
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from InsnBne import *
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from InsnBlt import *
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from InsnBge import *
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from InsnBltu import *
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from InsnBgeu import *
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from InsnLb import *
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from InsnLh import *
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from InsnLw import *
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from InsnLbu import *
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from InsnLhu import *
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from InsnSb import *
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from InsnSh import *
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from InsnSw import *
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from InsnAddi import *
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from InsnSlti import *
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from InsnSltiu import *
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from InsnXori import *
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from InsnOri import *
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from InsnAndi import *
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from InsnSlli import *
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from InsnSrli import *
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from InsnSrai import *
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from InsnAdd import *
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from InsnSub import *
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from InsnSll import *
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from InsnSlt import *
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from InsnSltu import *
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from InsnXor import *
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from InsnSrl import *
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from InsnSra import *
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from InsnOr import *
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from InsnAnd import *
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"""
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RV32I Base ISA
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"""
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class IsaRV32I(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
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# Core-specific constants
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
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# Input ports
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self.rvfi_valid = Signal(1)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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if self.RISCV_FORMAL_CSR_MISA:
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self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
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# Output ports
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if self.RISCV_FORMAL_CSR_MISA:
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self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_valid = Signal(1)
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self.spec_trap = Signal(1)
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self.spec_rs1_addr = Signal(5)
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self.spec_rs2_addr = Signal(5)
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self.spec_rd_addr = Signal(5)
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self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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self.rvfi_insn,
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self.rvfi_pc_rdata,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_rdata,
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self.rvfi_mem_rdata
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]
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if self.RISCV_FORMAL_CSR_MISA:
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input_ports.append(self.rvfi_csr_misa_rdata)
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output_ports = [
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self.spec_valid,
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self.spec_trap,
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self.spec_rs1_addr,
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self.spec_rs2_addr,
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self.spec_rd_addr,
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self.spec_rd_wdata,
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self.spec_pc_wdata,
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self.spec_mem_addr,
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self.spec_mem_rmask,
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self.spec_mem_wmask,
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self.spec_mem_wdata
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]
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if self.RISCV_FORMAL_CSR_MISA:
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output_ports.append(self.spec_csr_misa_rmask)
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return input_ports + output_ports
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def elaborate(self, platform):
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pass
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@ -0,0 +1,110 @@
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RV32I_INSNS = [
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'lui',
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'auipc',
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'jal',
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'jalr',
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'beq',
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'bne',
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'blt',
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'bge',
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'bltu',
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'bgeu',
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'lb',
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'lh',
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'lw',
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'lbu',
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'lhu',
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'sb',
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'sh',
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'sw',
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'addi',
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'slti',
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'sltiu',
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'xori',
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'ori',
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'andi',
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'slli',
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'srli',
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'srai',
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'add',
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'sub',
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'sll',
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'slt',
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'sltu',
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'xor',
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'srl',
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'sra',
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'or',
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'and'
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]
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if __name__ == '__main__':
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print('# Generated by IsaRV32IGen.py')
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for insn in RV32I_INSNS:
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print('from Insn%s import *' % insn.capitalize())
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print()
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print('"""')
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print('RV32I Base ISA')
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print('"""')
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print()
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print('class IsaRV32I(Elaboratable):')
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print(' def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):')
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print(' # Core-specific constants')
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print(' self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN')
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print(' self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN')
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print(' self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA')
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print()
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print(' # Input ports')
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print(' self.rvfi_valid = Signal(1)')
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print(' self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)')
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print(' self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' if self.RISCV_FORMAL_CSR_MISA:')
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print(' self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)')
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print()
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print(' # Output ports')
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print(' if self.RISCV_FORMAL_CSR_MISA:')
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print(' self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.spec_valid = Signal(1)')
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print(' self.spec_trap = Signal(1)')
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print(' self.spec_rs1_addr = Signal(5)')
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print(' self.spec_rs2_addr = Signal(5)')
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print(' self.spec_rd_addr = Signal(5)')
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print(' self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)')
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print(' self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))')
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print(' self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))')
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print(' self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)')
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print(' def ports(self):')
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print(' input_ports = [')
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print(' self.rvfi_valid,')
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print(' self.rvfi_insn,')
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print(' self.rvfi_pc_rdata,')
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print(' self.rvfi_rs1_rdata,')
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print(' self.rvfi_rs2_rdata,')
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print(' self.rvfi_mem_rdata')
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print(' ]')
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print(' if self.RISCV_FORMAL_CSR_MISA:')
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print(' input_ports.append(self.rvfi_csr_misa_rdata)')
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print(' output_ports = [')
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print(' self.spec_valid,')
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print(' self.spec_trap,')
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print(' self.spec_rs1_addr,')
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print(' self.spec_rs2_addr,')
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print(' self.spec_rd_addr,')
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print(' self.spec_rd_wdata,')
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print(' self.spec_pc_wdata,')
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print(' self.spec_mem_addr,')
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print(' self.spec_mem_rmask,')
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print(' self.spec_mem_wmask,')
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print(' self.spec_mem_wdata')
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print(' ]')
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print(' if self.RISCV_FORMAL_CSR_MISA:')
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print(' output_ports.append(self.spec_csr_misa_rmask)')
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print(' return input_ports + output_ports')
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print(' def elaborate(self, platform):')
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print(' pass')
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# TODO
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