diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py new file mode 100644 index 0000000..c66a33d --- /dev/null +++ b/insns/IsaRV32I.py @@ -0,0 +1,103 @@ +# Generated by IsaRV32IGen.py +from InsnLui import * +from InsnAuipc import * +from InsnJal import * +from InsnJalr import * +from InsnBeq import * +from InsnBne import * +from InsnBlt import * +from InsnBge import * +from InsnBltu import * +from InsnBgeu import * +from InsnLb import * +from InsnLh import * +from InsnLw import * +from InsnLbu import * +from InsnLhu import * +from InsnSb import * +from InsnSh import * +from InsnSw import * +from InsnAddi import * +from InsnSlti import * +from InsnSltiu import * +from InsnXori import * +from InsnOri import * +from InsnAndi import * +from InsnSlli import * +from InsnSrli import * +from InsnSrai import * +from InsnAdd import * +from InsnSub import * +from InsnSll import * +from InsnSlt import * +from InsnSltu import * +from InsnXor import * +from InsnSrl import * +from InsnSra import * +from InsnOr import * +from InsnAnd import * + +""" +RV32I Base ISA +""" + +class IsaRV32I(Elaboratable): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): + # Core-specific constants + self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN + self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN + self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA + + # Input ports + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) + self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) + if self.RISCV_FORMAL_CSR_MISA: + self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) + + # Output ports + if self.RISCV_FORMAL_CSR_MISA: + self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + if self.RISCV_FORMAL_CSR_MISA: + input_ports.append(self.rvfi_csr_misa_rdata) + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + if self.RISCV_FORMAL_CSR_MISA: + output_ports.append(self.spec_csr_misa_rmask) + return input_ports + output_ports + def elaborate(self, platform): + pass diff --git a/insns/IsaRV32IGen.py b/insns/IsaRV32IGen.py new file mode 100644 index 0000000..4383bae --- /dev/null +++ b/insns/IsaRV32IGen.py @@ -0,0 +1,110 @@ +RV32I_INSNS = [ + 'lui', + 'auipc', + 'jal', + 'jalr', + 'beq', + 'bne', + 'blt', + 'bge', + 'bltu', + 'bgeu', + 'lb', + 'lh', + 'lw', + 'lbu', + 'lhu', + 'sb', + 'sh', + 'sw', + 'addi', + 'slti', + 'sltiu', + 'xori', + 'ori', + 'andi', + 'slli', + 'srli', + 'srai', + 'add', + 'sub', + 'sll', + 'slt', + 'sltu', + 'xor', + 'srl', + 'sra', + 'or', + 'and' +] + +if __name__ == '__main__': + print('# Generated by IsaRV32IGen.py') + for insn in RV32I_INSNS: + print('from Insn%s import *' % insn.capitalize()) + print() + print('"""') + print('RV32I Base ISA') + print('"""') + print() + print('class IsaRV32I(Elaboratable):') + print(' def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):') + print(' # Core-specific constants') + print(' self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN') + print(' self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN') + print(' self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA') + print() + print(' # Input ports') + print(' self.rvfi_valid = Signal(1)') + print(' self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)') + print(' self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)') + print() + print(' # Output ports') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_valid = Signal(1)') + print(' self.spec_trap = Signal(1)') + print(' self.spec_rs1_addr = Signal(5)') + print(' self.spec_rs2_addr = Signal(5)') + print(' self.spec_rd_addr = Signal(5)') + print(' self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)') + print(' self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') + print(' self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') + print(' self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)') + print(' def ports(self):') + print(' input_ports = [') + print(' self.rvfi_valid,') + print(' self.rvfi_insn,') + print(' self.rvfi_pc_rdata,') + print(' self.rvfi_rs1_rdata,') + print(' self.rvfi_rs2_rdata,') + print(' self.rvfi_mem_rdata') + print(' ]') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' input_ports.append(self.rvfi_csr_misa_rdata)') + print(' output_ports = [') + print(' self.spec_valid,') + print(' self.spec_trap,') + print(' self.spec_rs1_addr,') + print(' self.spec_rs2_addr,') + print(' self.spec_rd_addr,') + print(' self.spec_rd_wdata,') + print(' self.spec_pc_wdata,') + print(' self.spec_mem_addr,') + print(' self.spec_mem_rmask,') + print(' self.spec_mem_wmask,') + print(' self.spec_mem_wdata') + print(' ]') + print(' if self.RISCV_FORMAL_CSR_MISA:') + print(' output_ports.append(self.spec_csr_misa_rmask)') + print(' return input_ports + output_ports') + print(' def elaborate(self, platform):') + print(' pass') + # TODO