From 1c0541cd12c888c6a5e63bd416a1f76342489b55 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 16:06:15 +0800 Subject: [PATCH] Document RV32I R-Type Instructions --- insns/InsnAdd.py | 4 ++++ insns/InsnAnd.py | 4 ++++ insns/InsnOr.py | 4 ++++ insns/InsnSll.py | 4 ++++ insns/InsnSlt.py | 4 ++++ insns/InsnSltu.py | 4 ++++ insns/InsnSra.py | 4 ++++ insns/InsnSrl.py | 4 ++++ insns/InsnSub.py | 4 ++++ insns/InsnXor.py | 4 ++++ insns/README.md | 11 +++++++++++ 11 files changed, 51 insertions(+) diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py index 16d2de3..018afbc 100644 --- a/insns/InsnAdd.py +++ b/insns/InsnAdd.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +ADD instruction +""" + class InsnAdd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) diff --git a/insns/InsnAnd.py b/insns/InsnAnd.py index 0194446..e0f4adb 100644 --- a/insns/InsnAnd.py +++ b/insns/InsnAnd.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +AND instruction +""" + class InsnAnd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) diff --git a/insns/InsnOr.py b/insns/InsnOr.py index 241faa0..1470644 100644 --- a/insns/InsnOr.py +++ b/insns/InsnOr.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +OR instruction +""" + class InsnOr(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnOr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) diff --git a/insns/InsnSll.py b/insns/InsnSll.py index f825bb9..bb99acb 100644 --- a/insns/InsnSll.py +++ b/insns/InsnSll.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SLL instruction +""" + class InsnSll(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSll, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py index 7ba4b9e..4f2be0f 100644 --- a/insns/InsnSlt.py +++ b/insns/InsnSlt.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SLT instruction +""" + class InsnSlt(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) diff --git a/insns/InsnSltu.py b/insns/InsnSltu.py index aa2f207..318f717 100644 --- a/insns/InsnSltu.py +++ b/insns/InsnSltu.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SLTU instruction +""" + class InsnSltu(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) diff --git a/insns/InsnSra.py b/insns/InsnSra.py index bccf74b..bbdc626 100644 --- a/insns/InsnSra.py +++ b/insns/InsnSra.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SRA instruction +""" + class InsnSra(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py index 51c1b06..ad93d47 100644 --- a/insns/InsnSrl.py +++ b/insns/InsnSrl.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SRL instruction +""" + class InsnSrl(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) diff --git a/insns/InsnSub.py b/insns/InsnSub.py index 85bf28c..d8bf5fd 100644 --- a/insns/InsnSub.py +++ b/insns/InsnSub.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +SUB instruction +""" + class InsnSub(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) diff --git a/insns/InsnXor.py b/insns/InsnXor.py index 4e08162..58c4978 100644 --- a/insns/InsnXor.py +++ b/insns/InsnXor.py @@ -1,5 +1,9 @@ from InsnRV32IRType import * +""" +XOR instruction +""" + class InsnXor(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): super(InsnXor, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) diff --git a/insns/README.md b/insns/README.md index a8ca67e..37bae7a 100644 --- a/insns/README.md +++ b/insns/README.md @@ -35,6 +35,17 @@ _Note: This section is under development and will be updated as more classes are implemented._ - `Insn`: General RISC-V instruction + - `InsnRV32IRType`: RV32I R-Type Instruction + - `InsnAdd`: ADD instruction + - `InsnSub`: SUB instruction + - `InsnSll`: SLL instruction + - `InsnSlt`: SLT instruction + - `InsnSltu`: SLTU instruction + - `InsnXor`: XOR instruction + - `InsnSrl`: SRL instruction + - `InsnSra`: SRA instruction + - `InsnOr`: OR instruction + - `InsnAnd`: AND instruction ## Parameters